Fix the following error detected by checkpatch.pl:
ERROR: space required before the open parenthesis '('
TEST=Build and run on Galileo Gen2
Change-Id: I4df0f7f6d62561044605616aa623c2cfc2ccfa50
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 45fde705b6
Original-Change-Id: I8953fecbe75136ff989c9e3cf6c5e155dcee3c3b
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18698
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/452883
Fix the following warning detected by checkpatch.pl:
WARNING: braces {} are not necessary for single statement blocks
TEST=Build and run on Galileo Gen2
Change-Id: I134962a8312abd8fc10392768102585299ed6094
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2f919ec476
Original-Change-Id: Ie4b41f6fb75142ddd75103a55e0347ed85e7e873
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18697
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452882
Fix the following errors detected by checkpatch.pl:
ERROR: "foo* bar" should be "foo *bar"
ERROR: "(foo*)" should be "(foo *)"
ERROR: "foo * const * bar" should be "foo * const *bar"
TEST=Build and run on Galileo Gen2
Change-Id: I81197767b99948c51846217cb63400b5c3ea7da5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b2d834a93a
Original-Change-Id: I0d20ca360d8829f7d7670bacf0da4a0300bfb0c1
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18696
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/452881
Fix the following warning detected by checkpatch.pl:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
The remaining 37 warnings in gcov-io.c and libgcov.c are all false
positives generated by checkpatch detecting a symbol or function name
ending in _unsigned.
TEST=Build and run on Galileo Gen2
Change-Id: I746e85924f2f4684e3b67941fdfa3e5084c498f7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 75b859978a
Original-Change-Id: I9f1b71993caca8b3eb3f643525534a937d365ab3
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18695
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/452880
Fix the following error detected by checkpatch.pl:
ERROR: space prohibited after that '&' (ctx:ExW)
TEST=Build and run on Galileo Gen2
Change-Id: I2e92383212828c67c4ac71d0d11acd7e5e190ffc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 18cb7e66bd
Original-Change-Id: Ied8b4c00fc57a35ed4d649264a5ff1b8dcc6a1cd
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18648
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/452878
Fix the following error detected by checkpatch.pl:
ERROR: space required after that ',' (ctx:VxV)
TEST=Build and run on Galileo Gen2
Change-Id: I4025b28b4479350718da5403a2eb6c3dc9804fe9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ae3fd34e00
Original-Change-Id: I297bfc3d03dc95b471d3bb4b13803e81963841b5
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18647
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/452877
Fix the following error and warning detected by checkpatch.pl:
ERROR: code indent should use tabs where possible
WARNING: please, no spaces at the start of a line
TEST=Build and run on Galileo Gen2
Change-Id: Ib4ccd723c74498beef266cc13ad428cfca7ddebd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 708fc274b5
Original-Change-Id: I487771b8f4d7e104457116b772cd32df5cd721a6
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18646
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/452476
Fix the following error detected by checkpatch.py:
ERROR: Macros with multiple statements should be enclosed in a do - while loop
False positives are generated when assembly code is used in a macro. An
example is:
ERROR: Macros with multiple statements should be enclosed in a do - while loop
+#define post_code(value) \
+ movb $value, %al; \
+ outb %al, $CONFIG_POST_IO_PORT
False positives are also generated for linker script include files. An
example is:
ERROR: Macros with multiple statements should be enclosed in a do - while loop
+#define SET_COUNTER(name, addr) \
+ _ = ASSERT(. <= addr, STR(name overlaps the previous region!));
\
+ . = addr;
False positives are also generated for attribute macros. An example is:
ERROR: Macros with multiple statements should be enclosed in a do - while loop
+#define DISABLE_TRACE_ON_FUNCTION __attribute__
((no_instrument_function));
TEST=Build and run on Galileo Gen2
Change-Id: Ie8ee87e4f64e1259d085ad562c7ea3e5c281a0a7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bb4ae07417
Original-Change-Id: I88abf96579e906f6962d558a3d09907f07d00b1c
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18644
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/452475
Fix the following error detected by checkpatch.pl:
ERROR: trailing statements should be on next line
TEST=Build and run on Galileo Gen2
Change-Id: If0becceb9b15ff43fd2e5114fa71ab2c5b496c73
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e0f5dfc678
Original-Change-Id: I169f520db6f62dfea50d2bb8fb69a8e8257f86c7
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18643
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/452474
Fix warning detected by checkpatch.pl:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
BRANCH=none
BUG=None
TEST=Build and run on Galileo Gen2
Change-Id: If4e006aff16981e2e9b7ac38ea2909838b2660d5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0ca2a0654c
Original-Change-Id: I23d9b4b715aa74acc387db8fb8d3c73bd5cabfaa
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18607
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/452473
Add two GPIO macros:
1. PAD_CFG_GPI_APIC_EDGE allows a pin to be route to the
APIC with input assuming the events are edge triggered.
2. PAD_CFG_GPI_ACPI_SCI_LEVEL to route the general purpose
input to SCI assuming the events are level triggered.
BUG=none
BRANCH=none
TEST=none
Change-Id: I38f8bb09537eaf41c89d584db767bda484181416
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 75d8d8da47
Original-Change-Id: I944a9abac66b7780b2336148ae8c7fa3a8410f3f
Original-Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18533
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/452472
Add SKL/KBL PCH-H GPIO settings referring from SKL PCH-H
specifications to support sklrvp11.
Split the gpio_defs.h into headers gpio_pch_h_defs.h and
gpio_soc_defs.h for PCH-H specific and SOC specific GPIO
defs respectively.
BUG=none
BRANCH=none
TEST=none
Change-Id: I598225ee81d49b70965374bb888d3e3ad3c600bb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6a740539d1
Original-Change-Id: I5eaf8d809a1244a56038cbfc29502910eb90f9f2
Original-Signed-off-by: Li Cheng Sooi <li.cheng.sooi@intel.com>
Original-Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18027
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/452471
In all simplicity, with board/OptionsIds.h file having:
IDSOPT_IDS_ENABLED TRUE
IDSOPT_TRACING_ENABLED TRUE
And src/Kconfig modified to:
config WARNINGS_ARE_ERRORS
default n
With these settings AGESA outputs complete debugging log
where-ever you have your coreboot console configured.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id2a2b54b1aa2d2ad497b2fa25f418c52244c3fb3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 86ee4db0d8
Original-Change-Id: Ie5c0de6358b294160f9bf0a202161722f88059c1
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15320
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452470
We have been forced to build AGESA with ASSERT() as non-fatal
for some board, as hitting those errors is not uncommon.
For the cases touched here, abort eventlog operations early
to avoid further errors and dereference of null pointers.
BUG=none
BRANCH=none
TEST=none
Change-Id: I342e3195585ca435749886e990b40ea65e2bd311
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bfa72ce23b
Original-Change-Id: I1a09ad55d998502ad19273cfcd8d6588d85d5e0c
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18543
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/452468
Implement threshold as described in AMD.h, and do not add
entries below STATUS_LOG_LEVEL in the eventlog.
BUG=none
BRANCH=none
TEST=none
Change-Id: I41a257d8482bdeb568689045511547484c33e3c0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4f74c89592
Original-Change-Id: Ic9e45b1473b4fee46a1ad52d439e8682d961dc03
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18542
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/452466
This is useful for debugging S3 issues and in general
to understand AGESA memory allocator behaviour.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6537ba637e2e7adbaf0f82481ff75cd4cfd110c1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 50e6daff95
Original-Change-Id: I422f2620ed0023f3920b8d2949ee1c33a6c227e0
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18535
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452465
A problem around CAR teardown time may result with missing
training results at the time we want to save them.
Record this in the logs for debugging purposes, it will
not be possible to use S3 suspend if this happens.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1be67747db636b92ddc7c38d2d851ce81b7b359d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 86690eb0a1
Original-Change-Id: Id2ba8facbd5d90fe3ed9c6900628309c226c2454
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18534
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-on: https://chromium-review.googlesource.com/452464
When allowing use of SSE instructions, stack must be
aligned to 16 bytes. Adjust x86 entry to C accordingly,
by pushing values to maintain the alignment.
Fixes regression with new toolchain using GCC-6.3 and
ec0a393 console: Enable printk for ENV_LIBAGESA
For some builds, the above-mentioned commit emitted
SSE instruction 'andps (%esp),%xmm0' with incorrectly
aligned esp, raising exception and thus preventing boot.
BUG=none
BRANCH=none
TEST=none
Change-Id: I5384281bdb98775fc6537734172c515eda58925a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 26929bd71a
Original-Change-Id: Ief57a2ea053c7497d50903838310b7f7800bff26
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18622
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/452463
The init files for the Core Duo and Core 2 Duo are very similar. Reduce
the differences, by using the same order for the include statements, the
same blank lines, and the same comments.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2ac2f5eda9f6d2dcc475d9363496dbcd26b9d03b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7129ccbd23
Original-Change-Id: I0de060222a61a482377c760c6031d73c7e318edf
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/18506
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/452461
This is required to transmit button information from EC to kernel.
BUG=b:35774934
BRANCH=None
TEST=Verified using evtest that kernel is able to get button
press/release information from EC.
Change-Id: I754490b80a191d298d748d21a3e8d5407a7895dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a89254801c
Original-Change-Id: I8f380f935c2945de9d8e72eafc877562987d02db
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18642
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452372
This is required to pass button information from EC to kernel without
using 8042 keyboard driver.
1. Define EC buttons device using GOOG0007 ACPI ID.
2. Guard enabling of this device using EC_ENABLE_MKBP_DEVICE.
BUG=b:35774934
BRANCH=None
TEST=Verified using evtest that kernel is able to get button
press/release information from EC.
Change-Id: I30e42c66dec3a639c172df465a98e8bb9c03ebdd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d4a0a348e4
Original-Change-Id: I4578f16648305350d36fb50f2a5d2285514daed4
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18641
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452371
Apollolake platform comes with FPF (field-programmable-fuses). FPF can
be blown only once, typically at the end of the manufacturing process.
This patch adds code that sends a request to CSE to figure out if FPFs
have already been blown.
BUG=none
BRANCH=none
TEST=none
Change-Id: I45d74923d7b4dc8adb8bfa812965694abd75d5ee
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b1aded2f0c
Original-Change-Id: I9e768a8b95a3cb48adf66e1f17803c720908802d
Original-Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18604
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452370
Add common driver that can send/receive HECI messages. This driver is
inspired by Linux kernel mei driver and somewhat based on Skylake's.
Currently it has been only tested on Apollolake.
BUG=b:35586975
BRANCH=reef
TEST=tested on Apollolake to send single messages and receive both
fragmented and non-fragmented versions.
Change-Id: Ia22e402e626e4da9dd75c934cbf0e142d1ec990e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 04a72c4019
Original-Change-Id: Ie3772700270f4f333292b80d59f79555851780f7
Original-Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18547
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452368
The __attribute__((weak)) lines on structs were being read as functions,
causing a warning that the brace should be on the next line.
Add a check to see if it's a struct with an attribute, and ignore it for
the OPEN_BRACE check if it is.
BUG=none
BRANCH=none
TEST=none
Change-Id: I69e9577374579bf24736b2961285938c124df8c0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 010905ed2f
Original-Change-Id: Ieb0c96027e8df842f60ca7c9de7aac941eed1dc2
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18570
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/452366
- Remove the "MISSING_SPACE" check which checks for breaks at a space in
a string concatenation. Most of the time this makes sense, but we
occasionally need to break where there isn't a space, so having a hard
rule doesn't always work.
- Don't check the vendorcode directory for compliance to coreboot's
code format rules.
BUG=none
BRANCH=none
TEST=none
Change-Id: If6648109dac8e91066f03e8d3c733db2f239b978
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2e17eaed1b
Original-Change-Id: Ic07677b19520b5d22363834c77f5dee7bba9e429
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18569
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/452365
checkpatch: add option for excluding directories
when importing code from external sources
Using --exclude <dir> we should be able to exclude a list of well
defined locations in the tree that carry sources from other projects
with other styles.
This comes from the 01org/zephyr project in github:
Original-Change-Id: I7d321e85eed6bc37d5c6879ae88e21d20028a433
Original-Signed-off-by: Anas Nashif <anas.nashif@intel.com>
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifdd76bc8f440e6cbb478fabd3b1a7bce55d1009f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a3cac87ea8
Original-Change-Id: Icc9e841e7d84026d6ab857ff90b0f093515ccaad
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18568
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/452364
Fix the following errors detected by checkpatch.pl:
ERROR: space prohibited after that open parenthesis '('
ERROR: space prohibited before that close parenthesis ')'
TEST=Build and run on Galileo Gen2
Change-Id: I06aa831a79cb531d5b7042b72950c7a79fe445c4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d638ef4ec4
Original-Change-Id: I586c5731c080282080fe5ddf3ac82252cb35bdd4
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18636
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/452363
The event log entry indicating developer mode is useful for the
boot path, but is not really useful on the resume path and removing
it makes the event log easier to read when developer mode is enabled.
To make this work I have to use #ifdef around the ACPI code since
this is shared with ARM which does not have acpi.h.
BUG=b:36042662
BRANCH=none
TEST=perform suspend/resume on Eve and check that the event log
does not have an entry for Chrome OS Developer Mode.
Change-Id: Ief6dead73856689f0fb0bce6266d66c7196340ee
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f8401cddb8
Original-Change-Id: I1a9d775d18e794b41c3d701e5211c238a888501a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18665
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452361
If Deep Sx is enabled the event log will get entries added on every
power sequence transition indicating that the suspend well has failed.
When a board is using Deep Sx by design this is intended behavior and
just fills the logs with extraneous events.
To make this work the device init state has to be executed first so it
actually enables the Deep Sx policies in the SOC since this code does
not have any hooks back into the devicetree to read the intended setting
from there.
BUG=b:36042662
BRANCH=none
TEST=Perform suspend/resume on Eve device with Deep S3 enabled, and
then check the event log to be sure that it does not contain the
"SUS Power Fail" event.
Change-Id: I8455c68e305a3c098d6a823c1586a8db77c88666
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ac2cbd0ffb
Original-Change-Id: I3c8242baa63685232025e1dfef5595ec0ec6d14a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18664
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/452360
Add a function to read the current state of Deep S5 configuration
and indicate if it is enabled (for AC and/or DC) or disabled.
This is similar to the existing function that checks Deep S3
enable state.
BUG=b:36042662
BRANCH=none
TEST=tested with subsequent commits to check Deep S5 state at boot
and filter event log messages if it is enabled.
Change-Id: I5aaa847908d0ab3468310e69414a08875777a78f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cb76d50f0d
Original-Change-Id: I4b60fb99a99952cb3ca6be29f257bb5894ff5a52
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18663
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/452359
Add options to the skylake chip config that will allow tuning the
various settings that can affect acoustics with the CPU and its VRs.
These settings are applied inside FSP, and they can adjust the slew
slew rate when changing voltages or disable fast C-state ramping on
the various CPU VR rails.
BUG=b:35581264
BRANCH=none
TEST=these are currently unused, but I verified that enabling the
options can affect the acoustics of a system at runtime.
Change-Id: I9445eb29c9f3089f68f1445fce8fb50464bf10cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b2aac85030
Original-Change-Id: I6a8ec0b8d3bd38b330cb4836bfa5bbbfc87dc3fb
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18662
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452358
A new board revision is making use of two previously unused GPIOs
to drive BOOT/RESET pins to an on-board MCU.
The reset pin is open drain so it is set as input by default, and
the boot pin is driven low by default.
Since these are UART0 pins they also need to be set up again after
executing FSP-S as it will change them back to native mode pins.
BUG=b:36025702
BRANCH=none
TEST=manual testing on reworked board, toggling GPIOs to put
the MCU into programming mode.
Change-Id: I3f6facc48a380e3e72e6832f9a5a9a1730d2f935
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 03df460af5
Original-Change-Id: Id6f0ef2f863bc1e873b58e344446038786b59d25
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18661
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452357
Allows to use SSE and floating point in payloads without digging to
much into x86 assembly code.
Tested on Lenovo T500 (Intel Core2Duo).
Both floating point operation and SSE is properly working.
BUG=none
BRANCH=none
TEST=none
Change-Id: I5869905873f0bacfeb38d7e81d25d956a676ffb5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b854ae2649
Original-Change-Id: I4a5fc633f158de421b70435a8bfdc0dcaa504c72
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18345
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/451619
Fine tune USB2, need to override the following registers.
port#1:
PERPORTPETXISET=7
PERPORTTXISET=0
BUG=b:35858164
BRANCH=reef
TEST=built, measured eye diagram on snappy, and reviewed by intel
Change-Id: Ic4964e78338cb6d00d8d2dd61d627870ad656882
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e4c85c128a
Original-Change-Id: I461cf8f032b4e70abc9707e6cd3603a62cee448f
Original-Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/18590
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/451617
This adds support for the Wildcat Point LP for intelmetool.
When the tool detected a Wildcat Point LP,
then the ME will be reported as difficult-to-remove.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib1fda21126fa807d0b8e1a9e5a90120424bcc9bc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8c247a2a79
Original-Change-Id: I35423db11cdc1e21e7f02ce90dace7fb4d236c45
Original-Signed-off-by: Huan Truong <htruong@tnhh.net>
Original-Reviewed-on: https://review.coreboot.org/18575
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/451436
The intel ME checker tool would segfault if it reaches the end of
the loop without having the dev pointer set. This happens when
it gets to the end of the previous loop without knowing what to do
with any of the devices it sees.
This patch makes sure the pointer is not NULL before accessing it.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibaef27c8be18b6704d60250098a6f676fe197965
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2a1ae05316
Original-Change-Id: Ia13191799d7e00185947f9df5188cb2666c43e2a
Original-Signed-off-by: Huan Truong <htruong@tnhh.net>
Original-Reviewed-on: https://review.coreboot.org/18573
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/451435
- Fix whitespace: Change some spaces to tabs
- Add myself as an abuild maintainer
- Add util/xcompile and util/genbuild_h to the BUILD SYSTEM section
- Add new sections for utilities: docker, toolchain, and git
- Remove GENERIC DRAM section
- Remove the mailing list. We don't want it to be added as a reviewer.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2dfae1e05e38a8d5bdba90cc5460f3ada6727ce1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 954338d21b
Original-Change-Id: I78692fcac174d7b7c4d65911c85e4e2dacefcfc0
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18578
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/451434
No board with binaryPI currently supports HAVE_ACPI_RESUME. For
platforms with PSP the approach is also very different from what
we previously had here.
Furthermore, s3_resume.[ch] files under cpu/amd/pi do not
distinguish between NonVolatile and Volatile buffers of S3 storage.
This means the Volatile buffer that is maintained and available in
CBMEM is unnecessarily copied to SPI flash. This has been fixed on
open-source AGESA directory, so development of S3 suspend support
with binaryPI is better continued with that.
Unfortunately there are further complications and indications that
open-source AGESA may have always had a low-memory corruption
issue. This has to be investigated separately before restoring
or claiming S3 is supported on binaryPI.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iaa3b5135ab114cd1e0dcd540ed8df3adee235dcf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 97a4b3edf0
Original-Change-Id: I81585fff7aae7bcdd55e5e95bc373e0adef43ef0
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18501
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-on: https://chromium-review.googlesource.com/451433
None of the boards currently have HAVE_ACPI_RESUME and
and ACPI S3 support calls should not appear under board
directories anyways.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9b9d34bc46a403431f24abe42d1180a6cca6841c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1b183aa6ce
Original-Change-Id: I1abd40ddba64be25b823abf801988863950c1eb5
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18500
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-on: https://chromium-review.googlesource.com/451432
The file is used for fam15.
BUG=none
BRANCH=none
TEST=none
Change-Id: I52a113c24020e70ae237a97661ced1310c6f6185
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3444a9d716
Original-Change-Id: I7cdf238a8f7be4bf79546bcfc3c9d05bd8986e3e
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18635
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-on: https://chromium-review.googlesource.com/451431
