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UPSTREAM: google/eve: Configure GPIOs for new board

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A new board revision is making use of two previously unused GPIOs
to drive BOOT/RESET pins to an on-board MCU.

The reset pin is open drain so it is set as input by default, and
the boot pin is driven low by default.

Since these are UART0 pins they also need to be set up again after
executing FSP-S as it will change them back to native mode pins.

BUG=b:36025702
BRANCH=none
TEST=manual testing on reworked board, toggling GPIOs to put
the MCU into programming mode.

Change-Id: I3f6facc48a380e3e72e6832f9a5a9a1730d2f935
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 03df460af5
Original-Change-Id: Id6f0ef2f863bc1e873b58e344446038786b59d25
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18661
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452357
This commit is contained in:
Duncan Laurie 2017-03-07 18:59:19 -08:00 • committed by chrome-bot
commit 288e6e2808
1 changed files with 4 additions and 2 deletions
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6
src/mainboard/google/eve/gpio.h
View file

@ -105,8 +105,8 @@ static const struct pad_config gpio_table[] = {
/* SM1DATA */ PAD_CFG_NC(GPP_C7),
/* UART0_RXD */ PAD_CFG_GPI(GPP_C8, NONE, PLTRST), /* FP_INT */
/* UART0_TXD */ PAD_CFG_GPO(GPP_C9, 1, DEEP), /* FP_RST_ODL */
/* UART0_RTS# */ PAD_CFG_NC(GPP_C10),
/* UART0_CTS# */ PAD_CFG_NC(GPP_C11),
/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* PCH_FPS_MCU_NRST_ODL */
/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FPS_MCU_BOOT0 */
/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */
/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */
@ -234,6 +234,8 @@ static const struct pad_config early_gpio_table[] = {
static const struct pad_config late_gpio_table[] = {
/* UART0_RXD */ PAD_CFG_GPI(GPP_C8, NONE, PLTRST), /* FP_INT */
/* UART0_TXD */ PAD_CFG_GPO(GPP_C9, 1, DEEP), /* FP_RST_ODL */
/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* PCH_FPS_MCU_NRST_ODL */
/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FPS_MCU_BOOT0 */
};
#endif