With VPD blob of certain format, CBFS cache on storm proves to be not
large enough. This patch makes it bigger, it is still well above the
area preserved for the NSS.
BUG=chrome-os-partner:32152
TEST=the system now boots with the VPD it used to fail booting.
Change-Id: Ia88b598ad5e4b6adcbd87d865e43be57fbf0ea98
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219572
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Pass MAC addresses found in coreboot table into lib_sysinfo.
BUG=chrome-os-partner:32152
TEST=with all changes in place MAC addresses are properly inserted
into the kernel device tree.
Change-Id: I1d0bd437fb27fabd14b9ba1fb5415586cd8847bb
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219444
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Chrome OS devices firmware usually includes an area called VPD (Vital
Product Data). VPD is a blob of a certain structure, in particular
containing freely defined variable size fields. A field is a tuple of
the field name and field contents.
MAC addresses of the interfaces are stored in VPD as well. Field names
are in the form of 'ethernet_macN', where N is the zero based
interface number.
This patch retrieves the MAC address(es) from the VPD and populates
them in the coreboot table so that they become available to the
bootloader.
BUG=chrome-os-partner:32152, chromium:417117
TEST=with this and other patches in place the storm device tree shows
up with MAC addresses properly initialized.
Change-Id: I12c0d15ca84f60e4824e1056c9be2e81a7ad8e73
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219443
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Coreboot generic CBFS media API does not support
multiple media access instances, but it should.
With this fix the CBFS context (memory cache for
SPI accesses) is shared among all open media access
streams. A better memory management scheme might be
required, but for now this fix allows to support
booting deptcharge and accessing VPD through two
independent CBFS media streams.
BUG=chrome-os-partner:32152
TEST=no exception is thrown when the second stream
is opened
Change-Id: Ib9d9d1f5209c2e515a95d7acbf4a8ac1255d3f8a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219441
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Flashmap offset needs to be defined through
configuration option. This definition must match
the FMAP location defined the appropriate device
tree in the deptcharge repository.
BUG=chrome-os-partner:32152
TEST=attempts to look up VPD in flash map do not
fail anymore
Change-Id: I474f0c4854fc264bcae8eb27fbd43966a381aa91
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219440
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Cleanup of functions to write to clk_enb and rst_dev registers and addition of
clock_disable and clock_set_reset functions to provide a complete API for
updating the registers.
BUG=chrome-os-partner:31821
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt on ryu. Compiles
successfully on rush
Change-Id: Icb8081fe3d80174c920eaaecf5cbb0aa912d5b19
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/219191
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Since PSCI dynamically determines which EL to transition
to based on SCR_EL3 there's no need to provide that
information.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted into kernel with MP.
Change-Id: I8783b6315dca01464e14c9d2b20d009cf0beeb67
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218924
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The PSCI functionality initially includes CPU_ON and CPU_OFF
functions. Upon entering secmon the if the parameters are non-NULL
then a PSCI CPU_ON action is done for the current CPU.
BUG=chrome-os-partner:32112
BRANCH=None
TEST=Booted kernel with PSCI support. Brought up all CPUS in kernel
using PSCI. Turned CPUs on and off.
Change-Id: I943826b7dbcc8e3f6c8c4b66344af8fac12ba94e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218923
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
If an exception is taken that the secmon won't return
to there needs to be way to reset that cpu's state
w.r.t. stack usage. Therefore, provide secmon_trampoline
which will reinitialize the exception stack and SP_EL0
and start executing with SP_EL0 like the initial state
of the secmon entry.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted to kernel. Also tested when is PSCI
is employed in the kernel.
Change-Id: Ia3da75e1fa0251c8ea30eb0b0523c8a51c03b917
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218922
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Two things:
1. Not returning once setting the return state.
2. mempcy(x, y, ARRAY_SIZE(x)) is not memcpy(x, y, sizeof(x))
With these 2 changes arguments and results are being processed
correctly.
BUG=chrome-os-partner:32112
BRANCH=None
TEST=Built and brought up SMP using PSCI.
Change-Id: I656b9c11e3bc07cc1664789a600eb88afd639f93
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218847
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
BUG=None
TEST=Modify settings, build and update the image to Samus and
check the settings are applied to Registers.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Change-Id: I3d407b8f1cb4a6ea3d6879a8581156a73f98220f
Reviewed-on: https://chromium-review.googlesource.com/219073
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Do the absolute minimum needed to allow the DPAUX mux ctl write
for I2C6. This leaves HOST1X off (reset and clock disabled) to
avoid a conflict with any kernel display driver init.
I2C6 init/enable will be moved to ramstage in the next CL.
BUG=chrome-os-partner:31820
BRANCH=none
TEST=Dumped Speaker Driver (AD SSM4567) regs on Ryu, looks good.
Change-Id: I0760222f1d7ccee207ae9871aeed3e2ddbca3dca
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/218900
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to process PSCI commands SMC instructions need to be
serviced. Provide a simple way for users of SMC to register their
handlers by function.
The SMC layer hooks into the exception processing, however it only
processes AARCH64 SMC calls. All others are ignored.
BUG=chrome-os-partner:32112
BRANCH=None
TEST=Added nop smc call to depthcharge. SMC handled and continue booting
to kernel.
Change-Id: Ieaa29fa883b9f9d55fc62ba92a1d45452296efa4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218846
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
The exception vectors were not reinitialized in secmon yet.
Add that as well as the split BSP vs non-BSP path. In doing
so bring in the cpu.c semantics for determining bsp at runtime.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted to kernel. Also noted only one CPU
printing messages.
Change-Id: Ide66f13c24f5798d5983c481ce616ae2800d558c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218845
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
mosys will use this field to identify system
BRANCH=none
BUG=chromium:359155
TEST=build ok, make sure mosys can be executed on Auron
use dmidecode to check data is written correctly
Signed-off-by: Kane Chen <kane.chen@intel.com>
Change-Id: I597e78251250e26c02b13636e9a220a150dfa6ce
Reviewed-on: https://chromium-review.googlesource.com/217493
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Kane Chen <kane.chen@intel.com>
Commit-Queue: Kane Chen <kane.chen@intel.com>
It's helpful to differentiate the startup paths for
the BSP and the non-BSP. Therefore have c_entry
be an 2 element array of function pointers. The
non-BSP paths have an entry point one instruction after
stage/module entry.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted to kernel.
Change-Id: Ia573b1095dca5f69e371bf1ddf6b6df72fa3b52e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218844
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
BUG=chrome-os-partner:32112
BRANCH=None
TEST=Built secmon which had this type of relocation.
Change-Id: If170d9e270daf3153e92d16c06516915c727e930
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218843
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The cpu.c contains some helpful construts as well as ramstage
devicetree handling. Split the 2 pieces so that cpu.c can be
reused in secmon.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted.
Change-Id: Ie87bd35bf1ccd777331250dcdaae07dab82d3d18
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218842
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
In order to not break FAFT, and to have a quicker recovery
mode boot, reboot the PD controller into RO image in romstage.
This is done before the EC since rebooting the EC into RO will
also reboot the host.
BUG=chrome-os-partner:30079
BRANCH=none
TEST=boot samus EVT into recovery with 'dut-control power_state:rec'
and ensure that the PD controller is rebooted to RO in romstage.
Change-Id: I633f51afc382a7faab825c15618c0bc7566c4395
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218904
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
currently, if the cache size is, for example, 4096 byte, mapping 4096 byte data
fails due to the overly strict check. this change allows cbfs_simple_buffer_map
to use all the cache space to the last byte.
BUG=None
TEST=Booted Nyan Blaze.
BRANCH=None
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I0797b5010afd7316fdec605784e8f48e2d62c37f
Reviewed-on: https://chromium-review.googlesource.com/218883
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Coreboot needs to be able to reboot the PD controller into RO
image in recovery mode early in the boot process in order to
avoid a lengthy recovery mode boot if it is only done at vboot
software sync time.
In order to do this a new device index field is added to the
command structure which must be initaalized to zero for all EC
transactions.
This early init and image check code is only used in romstage so
include it in the __PRE_RAM__ block.
BUG=chrome-os-partner:30079
BRANCH=none
TEST=build and boot on samus EVT in recovery mode and see that
the PD is rebooted to RO mode early in the boot.
Change-Id: Iebc48709b527d3571618da775c849e1c3fcd6384
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218903
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to talk to the PD controller with a passthru command
coreboot needs to be able to use v3 commands.
The command version is automatically detected based on the
advertized flags from the EC.
BUG=chrome-os-partner:30079
BRANCH=none
TEST=boot on samus EVT
Change-Id: I94ace7741c9cd592921625fb793787247a5ca2aa
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218902
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
this change syncs the i2c driver with the one in depthcharge.
BUG=None
TEST=Booted Veyron Pinky
BRANCH=None
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I0d0fdefa58c5b4cc5c991be40796a800ccf074a5
Reviewed-on: https://chromium-review.googlesource.com/218873
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Bootblock stack on Danube should be SRAM and defined separately from
the rest of the coreboot stack. The actual coreboot stack will be
defined later.
The top of the stack should be above the bottom, as the stack grows
towards lower addresses.
BUG=chrome-os-partner:31438
TEST=ran bootblock on simulator under codescape, observed stack
properly initialized.
Change-Id: I3c37c8b5a1c0e7fd19411558a8f6d899fc283191
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218732
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
mosys will use this field to identify system
BRANCH=none
BUG=chromium:359155
TEST=build ok, use dmidecode to check whether data is
written correctly
Change-Id: Icfbd4c61fc49a9cb3d3ecd2b622339957963150c
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/217400
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
The Rk808 PMIC is a part that will probably be used by most Rk3288
boards, so it makes sense to keep it as common code in the the SoC
directory. This patch puts LDO control functions into rk3288/rk808.c, so
that the mainboard only has to call a simple interface to set up the
specific LDOs it requires.
BUG=chrome-os-partner:30167
TEST=Booted both this and the old version with a stubbed-out
i2c_writeb(), ensured that the final values are the same.
Change-Id: Ic172f9c402e829995f049726d3cb6dbd637039d1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217598
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to build upon the arm64 exception handlers need
to be registered. This provides very basic support to
register a handler for a specific exception vector.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted into kernel.
Change-Id: I0f68a48101ff48d582f5422871b9e7e5164357e4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218650
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
With the generic spintable support in place, use that.
BUG=chrome-os-partner:32082
BRANCH=None
TEST=None
Change-Id: Ic9949144ed1e9a952290d50b6726bf5891547896
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218657
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
With the generic spintable support in place, use that.
BUG=chrome-os-partner:32082
BRANCH=None
TEST=Booted into kernel.
Change-Id: Id0832a4553101a366f011099e0744f6630d91924
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218656
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Support the generic spintable code intead of having
the one-off implementation.
BUG=chrome-os-partner:32082
BRANCH=None
TEST=Built and booted to kernel w/ smp. Both w/ and w/o secure monitor.
Change-Id: I24d56a30fdabd7a35ebc28dcc355c675de823a51
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218655
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
There was a hacky and one-off spintable support in tegra132.
Make this support generic for all arm64 chips.
BUG=chrome-os-partner:32082
BRANCH=None
TEST=Ran with and without secure monitor booting smp into the kernel.
Change-Id: If12083a9afc3b2be663d36cfeed10f9b74bae3c8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218654
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
It's helpful to know if the current running CPU
is the BSP. Therefore, provide that semantic.
BUG=chrome-os-partner:32082
BRANCH=None
TEST=Built and booted to kernel.
Change-Id: I3d5518d1f6d6a78b14f25bb7ef79727605064561
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218653
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
In order to provide richer semantics for running code
on all CPUs add an all-but-self construct.
BUG=chrome-os-partner:32082
BRANCH=None
TEST=Built and booted to kernel.
Change-Id: Id18dc0423bcb0016ed36ace659b3f858e824c46c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218652
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Chapter 3.1 "Periodic Frame List" of EHCI 1.0 specification says
"Frame List Link pointers always reference memory objects that are
32-byte aligned."
jwerner@chromium.org suggests setting it to be 64-byte aligned for
consistency with other EHCI queue structures.
BUG=chrome-os-partner:31993
TEST=Tested on nyan platform. Before adding patch, USB keyboard behind
an external hub is not working to switch between "Default Locale" and
"English" (after pressing ESC+REFRESH+POWER on embedded keyboard and
later Left/Right-Arrow key on USB keyboard).
Change-Id: If52ddc43ebd5d509c19f104928dced5bd09b1706
Signed-off-by: Jim Lin <jilin@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/218403
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Report PCI routing table of all PCIe root ports for legacy interrupt.
Some PCIe devices using legacy interrupt can't work if PCI routing table
isn't defined. It's necessary and defined in BWG Chapter 28.1.3.
BUG=chrome-os-partner:31943
TEST=compiled and tested
BRANCH=NONE
Signed-off-by: Ted Kuo <tedkuo@ami.com.tw>
Change-Id: Ia15ced6c5fdcc6712e5f2831e42c6dee320f166b
Reviewed-on: https://chromium-review.googlesource.com/218422
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Ted Kuo <tedkuo@ami.com.tw>
Commit-Queue: Ted Kuo <tedkuo@ami.com.tw>
Tested-by: Ted Kuo <tedkuo@ami.com.tw>
Secure monitor runs at EL3 and is responsible for jumping to the payload at
specified EL and also to manage features like PSCI.
Adding basic implementation of secure monitor as a rmodule. Currently, it just
jumps to the the payload at current EL. Support for switching el and PSCI will
be added as separate patches.
CQ-DEPEND=CL:218300
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles succesfully and secure monitor loads and runs payload on ryu
Change-Id: I86d5e93583afac141ff61475bd05c8c82d17d926
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/214371
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
stage_entry is the best place to enter for secmon, since it sets up all the
stacks right. The only need we need to take care is losing out on the parameter
passed to secmon. This patch adds an entry point for secmon rmodule and moves
the argument from x0 to x25, which is restored just before the jump to c_entry
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully
Change-Id: I74a7a609fbc08692d68708abe132cd219c89b456
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/217570
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
this change makes cbfs able to load a decompressed stage to the load
address without using the cache. this reduces sram footprint in early
boot stages.
BUG=none
TEST=Booted veyron pinky and nyan blaze.
BRANCH=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: Ie60dbaedfa740b84037e7f059812dc5617ad8502
Reviewed-on: https://chromium-review.googlesource.com/217978
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Provide SCR_EL3 initialization on all CPUs. This settings were
chosen in such a way that nothing would need to be done if EL3
is abandoned after transitioning to EL2 or EL1. If persistent
EL3 program is used those SCR policies can be updated within
that program.
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Built and booted through kernel. Printed out SCR setting for
each CPU.
Change-Id: Id659f0a98360fe8bbc80e5a623eba1526e81b400
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218300
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
As the arm64 boot flow handles initializing the GIC by
way of the driver provide the SoC support for that
driver and use it.
BUG=chrome-os-partner:31945
BRANCH=None
TEST=Built and booted kernel on ryu.
Change-Id: I34efaf28369377f353b4c51d20d19c9433befda4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217514
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
For every CPU that comes online inialize the GIC for
that CPU. This allows the per-cpu register state to
be initialized for every CPU that comes online.
BUG=chrome-os-partner:31945
BRANCH=None
TEST=Built and booted to kernel on ryu.
Change-Id: I58d0ffcfe65cffc6a4dd2678c041219e1e698aaf
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217513
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The GIC is ARM's "Generic Interrupt Controller". This
change essentially implements the rudimentary support
for a GICv2 implementation that routes all interrupts
to Group1. This should also work for GICv1 with security
extensions.
BUG=chrome-os-partner:31945
BRANCH=None
TEST=Built and booted kernel using the code.
Change-Id: I4c5b84bfe888ac33fa01c8d64a3dffe1b5ddc823
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217512
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
