Baytrail: add _PRT to each PCIe root port device

Report PCI routing table of all PCIe root ports for legacy interrupt.
Some PCIe devices using legacy interrupt can't work if PCI routing table
isn't defined. It's necessary and defined in BWG Chapter 28.1.3.

BUG=chrome-os-partner:31943
TEST=compiled and tested
BRANCH=NONE
Signed-off-by: Ted Kuo <tedkuo@ami.com.tw>

Change-Id: Ia15ced6c5fdcc6712e5f2831e42c6dee320f166b
Reviewed-on: https://chromium-review.googlesource.com/218422
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Ted Kuo <tedkuo@ami.com.tw>
Commit-Queue: Ted Kuo <tedkuo@ami.com.tw>
Tested-by: Ted Kuo <tedkuo@ami.com.tw>

src/soc/intel/baytrail/acpi/pcie.asl

@@ -0,0 +1,109 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Intel SOC PCIe support */
+
+Device (RP01)
+{
+	Name (_ADR, 0x001c0000)
+
+	Method (_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				#undef PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D)
+			})
+		} Else {
+			Return (Package() {
+				#define PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D)
+			})
+		}
+	}
+}
+
+Device (RP02)
+{
+	Name (_ADR, 0x001c0001)
+
+	Method (_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				#undef PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, B, C, D, A)
+			})
+		} Else {
+			Return (Package() {
+				#define PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, B, C, D, A)
+			})
+		}
+	}
+}
+
+Device (RP03)
+{
+	Name (_ADR, 0x001c0002)
+
+	Method (_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				#undef PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, C, D, A, B)
+			})
+		} Else {
+			Return (Package() {
+				#define PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, C, D, A, B)
+			})
+		}
+	}
+}
+
+Device (RP04)
+{
+	Name (_ADR, 0x001c0003)
+
+	Method (_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				#undef PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, D, A, B, C)
+			})
+		} Else {
+			Return (Package() {
+				#define PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, D, A, B, C)
+			})
+		}
+	}
+}

src/soc/intel/baytrail/acpi/southcluster.asl

@@ -254,6 +254,9 @@ Device (IOSF)
 // IRQ routing for each PCI device
 #include "irqroute.asl"
 
+// PCI Express Ports 0:1c.x
+#include "pcie.asl"
+
 Scope (\_SB)
 {
 	// GPIO Devices