The TPM related files were moved into src/security/tpm in commit
64e2d19082 ("security/tpm: Move tpm TSS and TSPI layer to security
section"), then further work was done on the coreboot TPM stack which
makes it difficult to find the equivalent area of code which these files
correspond to.
Therefore, we will drop these files for now and leave it up to the
maintainers of VBOOT to re-add any TPM related files (if they want to)
in a future change.
Change-Id: Ief7cfb81efc4c3daadc4b73af21bfdf0224b9005
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This also adds a missing trailing '/' to util/gitconfig, as this is a
directory.
Change-Id: Ib45dbf161b773cd89ad5acee183aeceac4d29584
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89506
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was moved to commonlib in commit dc9f5cd546 ("coreboot: introduce
commonlib"), then subsequently moved into commonlib/bsd in
commit ea619425ee ("commonlib: Move commonlib/cbmem_id.h to commonlib/bsd/").
Change-Id: Ib92c89cd090e78c76931000925ea6292e1783e28
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89510
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was renamed to util/qualcomm in commit 101098c41a
("sdm845: Combine BB with QC-Sec for ROM boot").
Change-Id: I14c9b6d918d30e1d156559d110ad47e556645d84
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The E6400 and E7240 were updated to use a variant scheme in commit
f62734976c ("mb/dell: Convert E6400 into a variant") and commit
511872dae3 ("mb/dell: Convert Latitude E7240 into a variant"),
respectively, which changed the names of the directories they were
located in. Update MAINTAINERS to reflect this.
Change-Id: If35e5a0afe214fe623334e90969cc7f95d579a86
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
It makes it easier to request reviews on patches or report bugs.
Change-Id: Icaefa00c866ec6600637f67e7906f523b36348cb
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88276
Reviewed-by: KunYi Chen <kunyi.chen@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates the MAINTAINERS file to reflect active
maintenance for the Google Bluey mainboard and Qualcomm SOCs.
Specifically:
- A new section `GOOGLE BLUEY MAINBOARDS` is added, assigning
Subrata Banik and Kapil Porwal as maintainers for
`src/mainboard/google/bluey/`. This is for the newly
supported Bluey platform.
- A new section `QUALCOMM SOCS` is added, assigning Subrata
Banik and Kapil Porwal as maintainers for `src/soc/qualcomm/`.
Consequently, `src/soc/qualcomm/` is removed from the
`ORPHANED ARM SOCS` section. This establishes active support
for Qualcomm SOCs within coreboot.
Change-Id: I355fcf7a7c6c865a1cc3c405d5f8d03747b2d9fc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add GOOGLE OCELOT MAINBOARDS section for src/mb/google/ocelot and
update the maintainers list to add Nick Vaccaro, Pranava Y N, and
Avi Uday as maintainers.
Change-Id: Ia5fc7fcdd5ea2f3588343834dccd86ee2b17f9a8
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87438
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
- Update AMD maintainers lists to reflect current situation
- Remove Ron Minnich as maintainer (at his request)
- Update the Infrastructure owners to reflect the current situation.
Change-Id: I2feac94595081fcea9becd9d8067ddd99a50123c
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85883
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add Shuo to x86 maintainer to focus on x86 arch changes impacting
Xeon-SP.
Change-Id: Ia273f3d6fc1e4b13bd1f695976209a95adc03f60
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
It's too broken to be maintained.
Change-Id: I2c6492f4e37b21bdc2b8d413fb30beaf16403345
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
While I don't have +2 rights, I think it makes sense to add myself as
maintainer given I'm a creator of both ports in upstream tree.
Change-Id: I2484fc488040c2d86bbf3bf98f39354bf88efae8
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
I also add myself as the Maintainer for the SiFive boards, since I
happen to have both of them and I also ported the HiFive Unmatched to
coreboot.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ic0b8e1053c9f5007e29e997c1ff21ff4a496aea8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83697
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add GOOGLE FATCAT MAINBOARDS section for src/mb/google/fatcat and
update the maintainers list to add Subrata Banik and Pranava Y N
as maintainers
Change-Id: I5ae0f0d24d43e91c2097c68446bb64b9ae507e2e
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
I am the one who takes care of end to end DPTF (Thermal Management)
related coreboot things across various X86 based platforms.
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Change-Id: I08a1ae48bd5b66ee2f7903615e64d0bab5e0d7d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
All of the Dell Latitudes from GM45 and until at least Haswell use a
derivative of the MEC5035 EC, and I have been actively working on
coreboot support for this EC and boards that use it. Rename the "E6400
MAINBOARD" section to "DELL LATITUDE" and add mb/dell/snb_ivb_latitude
and mb/dell/e7240 as additional paths.
Change-Id: I7ba46980bfc8569a85593e415f01cc83fe7d67d7
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83008
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
That's an ATX mainboard with a LGA1150 socket and four DDR3 DIMM slots.
Porting was done using autoport and then doing a bunch of manual edits.
This board has two socketed DIP-8 SPI flash chips and a physical switch
to choose which one should the system boot from. As long as one of them
contains a bootable firmware image, it is possible to reflash the other
chip using the internal programmer by flipping the switch after booting
to OS. Even if one somehow manages to flash unbootable firmware to both
chips, they are socketed: one can carefully remove them from the socket
and reflash them externally, which is a relatively safe procedure (when
compared to in-circuit flashing, especially if the board isn't designed
to safely be flashed in-circuit). In short, the board is hard to brick.
Haswell MRC.bin cannot be used because it lacks support for the Z97 PCH
found on this mainboard. Broadwell MRC.bin only works with Haswell CPUs
so far, as raminit fails on Broadwell CPUs for an unknown reason. Maybe
it's something about RcvEn, but it's unlikely it can easily be fixed.
Working:
- All four DIMM slots
- Broadwell MRC.bin for raminit purposes
- Serial port to emit spam
- POST code display
- S3 suspend/resume
- All rear USB 3.0 ports
- Internal USB 2.0 port
- Audio output (green jack)
- Integrated graphics (libgfxinit)
- HDMI
- VBT
- Intel GbE (I218-V PHY and PCH MAC)
- Realtek RTL8111E GbE
- At least one SATA port
- M2_1 slot (Gen3 x4, bifurcated from CPU)
- Flashing internally with flashrom
- SeaBIOS (current version) to boot Arch Linux
- NCT6791D Super I/O software-based fan control
tested using `sensors` and `pwmconfig`, all 6
fan tachometers and 5 PWM outputs work fine.
Untested for now (i.e. should work, will eventually test):
- DVI-I, DisplayPort
- EHCI debug
- Front USB 2.0 and 3.0 ports
- The other audio jacks (as well as SPDIF)
- The other PCIe and M.2 ports
- Non-Linux OSes
- PS/2 combo port (can only test with a keyboard)
Untestable (i.e. cannot test due to unavailable hardware):
- Thunderbolt AIC (Add-In Card) support
Not working:
- Broadwell CPUs, they require more magic to work (working on it).
- Booting from ASM1062 SATA ports with SeaBIOS. Other payloads were
not tested. It seems that the problem is with the controllers.
- Super I/O automatic fan control: not yet implemented in coreboot.
To control fans, use software fan control methods in the meantime.
- Acer B247Y board driving a FHD panel of a Samsung S24E650 monitor,
connected to the board's HDMI output says "Unsupported resolution"
after libgfxinit configured the iGPU outputs in linear framebuffer
mode. HDMI output works fine after Linux's i915 driver takes over.
Not sure if it's specific to the monitor: the HDMI cable is beaten
up, and it is hard to replace (need to relocate the logic board so
that the ports are accessible).
Change-Id: If1d22547725e59f435de36b973e1bf4f334269a9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Máté Kukri <kukri.mate@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
It makes little sense to keep these around. Boards maintained on a
branch should use that branch's MAINTAINERS file instead, I'd say.
Change-Id: I670df889ffce82ee4ee4e2b91fe70f18adfcfdfa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
I am the one who takes care of most coreboot things for this board.
Change-Id: I1f587822d60d2f69f34f272685cad50149faf79b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Both boards are most certainly `Supported`, and have been for a long
time. I have no idea why they were labelled as `Maintained` instead.
Change-Id: I02a5979f094b507e9f7d758daf47eeb95064cf0d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82221
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When soc/amd/genoa was renamed to soc/amd/genoa_poc and mb/amd/onyx
was renamed to mb/amd/onyx_poc, the MAINTAINERS file wasn't updated, so
no reviewers were added automatically to patches on Gerrit that change
things in soc/amd/genoa_poc or mb/amd/onyx_poc. Fix this by updating the
folder names in the MAINTAINERS file too.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib52781ebc98bd2ce9df495526cfaf9d884aace50
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81679
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
