We'd been stopping the AVP by calling hlt, but this just puts it into a loop
which it busily executes forever. If the memory the loop is in is replaced,
however, the AVP will race off and do something random. It turns out that it
was writing the early parts of the rom stage into memory on top of the kernel
as it ran, either by coincidence or because it had rebooted and was actually
reloading the stage into memory.
Many thanks to Hung-Te for determining what was being overwritten by what
which helped determine who was doing the overwriting.
BUG=None
TEST=Before this change, booting in normal mode would cause the kernel to
behave strangely, often crashing. With this change, the kernel seems to boot
fine in normal mode.
BRANCH=None
Change-Id: I292c039c28691387e72386d2a9321c29437076ed
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/177086
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
These were a bit incomplete and weren't the same as the names in the manual.
The names for the event types were also a little too generic and might have
conflicted with other names. Also changed them from #defines to enums.
BUG=None
TEST=Built and booted on nyan.
BRANCH=None
Change-Id: I8b61e611fb599c0f989bd0ce246cb044464d1bd0
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/177085
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
This voltage is recommended for the CPU when running at 1.8GHz.
BUG=None
TEST=Built and partially booted on the new form factor nyan.
BRANCH=None
Change-Id: I4ae4b16179d1be241119d85986823ad52af4fb70
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/176906
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
The PMIC used on the older pixel based nyan boards and the newer boards are
different and use a different base offset for their voltage settings. We need
to set them to different values in order to get the correct voltage out.
BUG=None
TEST=With this and other changes, built and booted on old and new nyan boards.
BRANCH=None
Change-Id: Ie37b11802d8c08f07f37c350ceb732f519b69280
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/176905
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
The variable defaults to off because this will very much be the common case.
It's set to y in the nyan config at the moment, though, since the pixel
versions are the most common for now.
BUG=None
TEST=With this and other changes built and booted on old and new nyan boards.
BRANCH=None
Change-Id: Ib42c71e693663ccbea62fbabbc1500a1c7ecef24
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/176904
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
We're going to need some logic to decide what to set the PMIC registers to, so
we need to set the registers using code instead of an array. I never really
liked the array way of doing things anyway.
BUG=None
TEST=With this and other changes, built and booted on the new and old nyan
boards.
BRANCH=None
Change-Id: Ice7ee2830b1b24c25ac506ee004574eb861cf1c0
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/176903
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Add the chip option to disable SATA DEVSLP. This disables
the SDS bit in the SATA CAP2 register.
BUG=chrome-os-partner:23186
BRANCH=leon
TEST=Manual: System runs without SATA failure for more than 10 hours
Original-Change-Id: I8baa40935421769aeee341a78441fb19ecaa3206
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: https://chromium-review.googlesource.com/174648
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 49d25812b04a983d687a53a39530559ba99fd9b4)
Change-Id: Iac0b32f80958f5ffb571733484dc931bee216f55
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: https://chromium-review.googlesource.com/176352
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Print a space after a full stop.
BUG=none
TEST=boot tested
BRANCH=none
Change-Id: Ic7d0522ae35079b64ce61956d06ea59843ef9d80
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/176756
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
In the process of rewriting cbfstool for ARM and using
a new internal API a regression was introduced that would
silently let you add an ARM payload into an x86 CBFS image
and the other way around. This patch fixes cbfstool to
produce an error in that case again.
BRANCH=none
BUG=none
TEST=emerge-peach_pit with and without my other CL that fixes
the cbfs image type and see it fail without that CL.
Change-Id: I37ee65a467d9658d0846c2cf43b582e285f1a8f8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/176711
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
The TPM needs to have the TPM_Startup command sent to it
on all boot paths. The call init_chromeos() in romstage_common()
fulfills this requirement.
BUG=chrome-os-partner:24057
BRANCH=None
TEST=Built and booted. Was able to suspend to ram multiple times
in a row.
Change-Id: Id0339a9d82897249d20ff5f62d2dcb8b535310fa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176803
Reviewed-by: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Some of the drivers in the kernel were not so happy about
having shared IRQs. Also, sharing IRQs means more code
needs to be run in interrupt context to determine if the IRQ
was meant for a particular device. Fix this.
No more 'mmc1: got irq while runtime suspended' messages.
BUG=chrome-os-partner:24056
BRANCH=None
TEST=Built and booted. Looked at /proc/interrupts and noted no
more sharing between pci devices.
Change-Id: Ie5da102204ffe3156dd55ab17af77df245a57c97
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176792
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
The PCIe subsystem was constantly waking up boards from
S3 and S5. Completely disable PCIe wake ups. It can be made
mainboard-configurable later if needed.
BUG=chrome-os-partner:24004
BRANCH=None
TEST=Both S3 and EC RW->RW update (trip through S5) don't
cause wakeups.
Change-Id: I922e2947c4b6e29277d913f06192601a2954f8fe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176791
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Talking to David Chang, we decided to switch USB_ILIM_SEL
to low to allow the system to negotiate SDP/CDP with the
USB devices for the front USB ports.
BUG=none
BRANCH=none
TEST=boot tested on Beltino
Change-Id: Ib980100c648ae7472eac6f97e47f8ef3cbe72c7e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/176146
Reviewed-by: David Chang <davidchang@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
This writes the default value to the register, but it gets rid of
the error that disturbs some of our tests:
ERROR: PNP: 002e.4 70 irq size: 0x0000000001 not assigned
BRANCH=none
BUG=chrome-os-partner:23945
TEST=boot tested on Beltino
Change-Id: Ieab1c776b553c996a7d06e4059110943aaf41338
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/176145
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
The introduction of the buffer and cbfs_image api also
brought in some regressions, such as broken architecture
detection, that went undetected. This patch prepares
cbfstool for a fix.
- There has been a significant amount of dead code that
went undetected. Remove it!
- Fix a few shadowed variables
- Compile cbfstool with more warnings
BRANCH=none
TEST=build and boot coreboot on peach_pit and beltino
BUG=none
Change-Id: Ib6d02abd3ea404ec1e90f2acab6d7c67cac19220
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/176710
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Previously pads were being configured as both input and output
simultaneously due to the config bits being active low. Create new
defines that only enable either input or output, and use them in our
GPIO configs.
BUG=chrome-os-partner:22863
TEST=Manual on Rambi. Verify system boots and peripherals still
function.
BRANCH=None.
Change-Id: If386682a3d810864b7b9f5d2aecdb2e6cfceea86
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176725
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The kernel chromeos_laptop driver nomenclature expects the
board name to not be in all caps. Fix this as well as the i2c
address for the trackpad.
BUG=chrome-os-partner:24307
BRANCH=None
TEST=Built and booted. trackpad device is found. IRQs still not
working yet.
Change-Id: Id6be8ee4bce2835e303ea4fe63944be80d2d7ec2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176680
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
This commit does the common parts for all LPSS devices
that are enabled: enable snoop in IOSF and enable power
management. Additionally, the i2c devices are taken out of
reset.
BUG=chrome-os-partner:23790
BRANCH=None
TEST=Built and booted with modified kernel-next. I2C bus devices
show up and I see 0x10 on one of the buses.
Change-Id: I540caea6a8666f5684dc5cee683a6b085dfac6de
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176424
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Add the LPSS IOSF port access to reg_script. This is
going to be used by baytrail.
BUG=chrome-os-partner:23790
BRANCH=None
TEST=Buit.
Change-Id: I0367acdb584f2de0bb871b136042b57fe6b7ec90
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176423
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(panther port of I933c475f693b0271f86b5166eb2c9b3873f1c2c6)
BUG=none
BRANCH=none
TEST=boot test on panther
Change-Id: I5958a8d701901706eaa38df4323120c8352fea5c
Reviewed-on: https://chromium-review.googlesource.com/176563
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Mohammed Habibulla <moch@chromium.org>
Tested-by: Mohammed Habibulla <moch@chromium.org>
- NFC interrupt is expected in the kernel as a GPIO now,
so set it back to that type
- NFC FW update GPIO should be low
- Accel/Codec interrupts were still set as GPIO type,
they should be set as PIRQ type
BUG=chrome-os-partner:23752
BRANCH=samus
TEST=build and boot on samus proto1b
Change-Id: I354c848ae7b158943f4745872b82a49e17e67e2f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176513
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The eMMC device is initialized as version 4.5 with HS200 speeds.
BUG=chrome-os-partner:23966
BRANCH=None
TEST=Built and booted rambi to login screen off of eMMC device.
Change-Id: I686c6136005fcb2587b939ddea293f4398df9868
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176536
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The SSC (storage control cluster) houses the SD, SDIO, and eMMC
interfaces. The scc cofniguration function, baytrail_init_scc(),
is ran in the pre device stage to initialize the SCC. The eMMC
is expected to be configured for version 4.5.
BUG=chrome-os-partner:23966
BRANCH=None
TEST=Built and booted with some other eMMC changes into login screen off
of eMMC device.
Change-Id: I81cc755a790b7e43ad234a8201dae480277202c8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176535
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The SCORE allows controlling the pad configuration while
the SSC handles the configuration for the storage control
cluster.
BUG=chrome-os-partner:23966
BRANCH=None
TEST=Built.
Change-Id: Ifd9f67a4e88d5bb99faec6ceeb3e263001a87c41
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176533
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Also add the relevant info about these pins to the ASL tables + add
SMBIOS type 41 data for these parts.
BUG=chrome-os-partner:22863
TEST=Manual on Rambi. Set some pins to GPIO_DIRQ, and then verify DIRQ
regwrites w/ GPIO_DEBUG look correct.
Change-Id: Id40655f9fb2ea7b10e1ff58d0b2a8b4cc6f05ff8
Reviewed-on: https://chromium-review.googlesource.com/176299
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Add support for DirectIRQ / dedicated IRQs. This consists of up to 16
IRQs for both SCORE and SSUS banks.
BUG=chrome-os-partner:22863
TEST=Manual on Rambi. Set some pins to GPIO_DIRQ, and then verify DIRQ
regwrites w/ GPIO_DEBUG look correct.
Change-Id: I4b0dc6e7ae86c9f554b6e78792239234f702764c
Reviewed-on: https://chromium-review.googlesource.com/176165
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
For some reason HDA can now be disabled. It's unclear what changes
in the baytrail code allowed this to happen, sadly.
BUG=chrome-os-partner:22871
BRANCH=None
TEST=Noted hda is not in lspci.
Change-Id: I64e2560533be6f701fa66cd53c906b62b09012ed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176394
Rambi has 3 pins that need to be configured for SCI and SMI:
1. GPIO_CORE[0] - runtime SCI pin
2. GPIO_SUS[7] - SMI for firmware lid events
3. GPIO_SUS[0] - wake pin for S3 wakes from EC.
Configure these pins now that the rest of the infrastructure
is in place. The one thing that is yet to work is runtime SCI
for lid events once booted.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=built and booted. lid close at rec screen works. And wake
from S3 with a keyboard press works.
Change-Id: I5f8e38ec5f4cf1a8ef7aa7fcee9abc344d9b184f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176393
As rambi is a baytrail board it doesn't have a dedicated wake pin.
Therefore, one needs to enable the proper GPIO to wake up the sytem
before going into S3.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Put system into S3. Keyboard press created wake event. Also, typed
'lidclose' on EC console while at recovery screen. Machine properly
shutdown.
Change-Id: Ic67b6bce93d57c620f498505d83197e4ae34a07d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176392
GPIOs which trigger SMIs only set the status bits in the ALT_GPIO_SMI
regier. No bits in the SMI_STS register are set. Therefore, the
ALT_GPIO_SMI register needs to be read and cleared on every SMI.
Additionally, the mainboard_gpi_smi() handler needs to be called as
well on every SMI because of this property.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted to recovery screen. Typed 'lidclose' on EC
console. SMI occurred which caused the board to be shutdown.
Change-Id: Ic204d8b928a0cb4f51f108a649f374d9f94e4f47
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176391
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
In order for gpio pins to trigger an smi/sci the GPIO_ROUT
register needs to be set accordingly. For SMI, the ALT_GPIO_SMI
register needs to be enabled for each gpio as well.
The first 8 gpios from the suspend and core well are the only gpios
that can trigger an SMI or SCI. The settings for the GPIO_ROUT
and ALT_GPIO_SMI register are not commited until the SMM settings
are enabled in the southcluster.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted. Manually triggered SCI by changing GPE0a_EN
and toggling PCH_WAKE_L on the EC console.
Change-Id: Id79b70084edc39fc047475e984494c224bd75d6d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176390
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The clock output and I2S1 GPIO pins must be correctly configured so we can
initialize the audio system.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan
BRANCH=none
Change-Id: Ie0f283ab8948b0d9ac713eec3bc7c8ae72949330
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176212
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The "external peripheral 1" pinmux name should be changed as EXTPERIPH1.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan
BRANCH=none
Change-Id: I9d78e9dbdf9a94baf2a634c4dcf5c7cc6eca69ba
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176215
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
To enable audio playback, the I2S (currently only I2S1 is configured) and audio
codec (external peripheral 1) must be first configured.
Note due to Tegra1x4 audio hardware design, we need to enable all audio
peripherals on AHUB.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan; Able to readl(I2Sreg).
BRANCH=none
Change-Id: Ie5c8a95f385305870745af7aeb40d7f7da8bbc0b
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176104
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Some peripherals, like audio codecs, need clock outputs from Tegra chip.
The new clock_external_output(clk_id) allows enabling any of the three clock
outputs.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan
BRANCH=none
Change-Id: I05a1ffb80077d3b14751bfa0e7c47d541a103a08
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176108
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Drop a lot of u-boot-isms and share common TIS API
between I2C driver and LPC driver.
BUG=none
TEST=Boot tested on pit
BRANCH=none
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: I43be8eea0acbdaef58ef256a2bc5336b83368a0e
Reviewed-on: https://chromium-review.googlesource.com/175670
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
BUG=none
BRANCH=none
TEST=ran "cbmem" on nyan and saw timestamps.
Change-Id: Id1a0f32c4278e47b2f8c31492e87c0bc899adb50
Reviewed-on: https://chromium-review.googlesource.com/176172
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
For most Tegra peripherals the source clock mapping is the same. However for
some peripherals like HOST1X or AUDIO parts, the source ID has totally different
meanings. U-Boot solved this by creating a huge peripheral source clock table.
For Coreboot, since there are fewer peripherals to setup, we want to do this by
two APIs: clock_configure_source() for regular peripherals, and
clock_configure_irregular_source() for components with different clock source
mappings (you must find the real meanings in TRM).
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan
BRANCH=none
Change-Id: I7820768c577c8cfcccb6cbb14a5e0b1fe0fdc50f
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176109
The gpe0 block's size was being misreported. Correct
the gpe0 size and use make the FADT fields be more
robust instead instead of hand calculating fields that
are the based on the same size.
This change correctly enables GPE events in the kernel.
Confirmed this by using iotools read the gpe_cnt register.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted. Confirmed EC's GPE event is enabled (but
still not working).
Change-Id: I415710f7fec2e95cecee3bf679ee673dacc27480
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176271
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
- C-state table based on static config
MWAIT values are from ref code for non-S0ix config
C6 substate 8 is ignored by the kernel as it violates the CPUID
but it is left in as the other substate may not work.
- P-state table generated with proper ratio and VID values
relies on having the package power msr set to magic value
as the power-on default is wrong
- T-state table uses static table
BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi
Change-Id: I7c997e58cb3a71d0ec413b17f0c5467bef4bf62c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175742
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
The bus clock speed is needed when building ACPI P-state tables
so extract that function and have the value be saved in pattrs.
The various IACORE values are also needed, but rather than have
the ACPI code to the bit manipulation have the pattrs store an
array of the possible values for it to use directly.
BUG=chrome-os-partner:23505
BRANCH=none
TEST=build and boot on rambi
Change-Id: I5ac06ccf66e9109186dd01342dbb6ccdd334ca69
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176140
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
As far as I can tell turbo enabling behaves like
it did on haswell so use the standard code.
There are also some magic values to set in some magic
MSRs related to turbo and package power so they report
correctly.
The L2 cache shrink is enabled and a threshold is set
that makes both dual and quad core happy.
C1E is disabled to match the reference code.
BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi
Change-Id: Ic6d4283d480a44d85a9b96571baf83928615665c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175743
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
This required changing value/mask types to uint64_t.
Another option would be to use id field to select low or high
32 bits of the MSR and set them independently.
BUG=chrome-os-partner:23505
BRANCH=none
TEST=build and boot on rambi
Change-Id: Ied9998058a8035bf3f003185236f3be3e0df7fc9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176304
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Back when the code which got very basic things set up on the main CPUs was
committed, there was some late arriving review feedback that wasn't addressed.
This change goes back and addresses some of that feedback by renaming things
to maincpu instead of cpug, and reducing the alignment of the assembly.
The stack is still passed in from the C code because even though we always use
the same stack now, in the future we may want to start additional CPUs with
different stacks. I also kept the name maincpu_setup (originally cpug_setup)
instead of renaming it maincpu_enter because it should never be called
directly and doesn't "enter" the new CPU, it's run when the CPU comes out of
reset and gets some basic things setup for the main code written in C.
BUG=None
TEST=Booted on nyan.
BRANCH=None
Change-Id: Ia8e9fd07f9753f9ebcd51f29ca6876850f5380b7
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/175933
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
The superio.asl file allows for the mainboard to hang
devices off of the LPC bus in ACPI. Include the keyboard
controller, EC memory map, and host interface's resources.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted. Noted resource reservations in dmesg.
Change-Id: Ida6481cd4c4725b5d3946bc64179ee99c93b0106
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176134
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The mainboard needs an opportunity to hang devices off of
the LPC device. Therefore, provide this opportunity for the
mainboard.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Buit and booted with keyboard. Keys work.
Change-Id: Ie2b660ad43e86d9237b0b0bb0720b069670bc537
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176133
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Fix the SMI and SCI gpios for Rambi. Also, add in the
EC callbacks for the SMI handler. Note that the handler
for GPI SMIs has not been tested yet as baytrail chipset
code doesn't yet support setting up those configurations
yet.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Noted that SCI was enabled in /sys/firmware/acpi/interrupts
for the EC's SCI GPI. Also was able to see Chrome EC messages
with CONFIG_DEBUG_SMI and powering down at the dev screen.
Change-Id: I67b278fd38e1c09271d2c1e16e42f6e8c49e3a70
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176077
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
