samus: Misc fixes from proto1b bringup

- NFC interrupt is expected in the kernel as a GPIO now,
so set it back to that type
- NFC FW update GPIO should be low
- Accel/Codec interrupts were still set as GPIO type,
they should be set as PIRQ type

BUG=chrome-os-partner:23752
BRANCH=samus
TEST=build and boot on samus proto1b

Change-Id: I354c848ae7b158943f4745872b82a49e17e67e2f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176513
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2013-11-12 17:24:20 +08:00 committed by chrome-internal-fetch
commit 75a0944f32
2 changed files with 5 additions and 5 deletions

View file

@ -32,7 +32,7 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = {
LP_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */
LP_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */
LP_GPIO_ACPI_SCI, /* 8: PCH_LTE_WAKE_L */
LP_GPIO_PIRQ, /* 9: NFC_INT (PIRQJ) */
LP_GPIO_IRQ_EDGE, /* 9: NFC_INT (GPIO IRQ) */
LP_GPIO_ACPI_SCI, /* 10: PCH_WLAN_WAKE_L */
LP_GPIO_UNUSED, /* 11: UNUSED */
LP_GPIO_UNUSED, /* 12: UNUSED */
@ -87,7 +87,7 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = {
LP_GPIO_NATIVE, /* 61: NATIVE: PCH_SUS_STAT */
LP_GPIO_NATIVE, /* 62: NATIVE: PCH_SUSCLK */
LP_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */
LP_GPIO_OUT_HIGH, /* 64: NFC_FW_UPDATE */
LP_GPIO_OUT_LOW, /* 64: NFC_FW_UPDATE */
LP_GPIO_INPUT, /* 65: MINIDP_PWR_FLT_L */
LP_GPIO_OUT_HIGH, /* 66: MINIDP_PWR_EN */
LP_GPIO_INPUT, /* 67: RAM_ID0 */

View file

@ -41,13 +41,13 @@
#define BOARD_CODEC_NAME "codec"
#define BOARD_CODEC_IRQ 30 /* PIRQO */
#define BOARD_CODEC_IRQ_TYPE BOARD_GPIO_INTERRUPT
#define BOARD_CODEC_IRQ_TYPE BOARD_PIRQ_INTERRUPT
#define BOARD_CODEC_WAKE_GPIO 46 /* GPIO46 */
#define BOARD_CODEC_I2C_BUS 1 /* I2C0 */
#define BOARD_CODEC_I2C_ADDR 0x1a
#define BOARD_NFC_NAME "nfc"
#define BOARD_NFC_IRQ 25 /* PIRQJ */
#define BOARD_NFC_IRQ GPIO_INTERRUPT(9)
#define BOARD_NFC_IRQ_TYPE BOARD_GPIO_INTERRUPT
#define BOARD_NFC_WAKE_GPIO 9 /* GPIO9 */
#define BOARD_NFC_I2C_BUS 1 /* I2C0 */
@ -55,7 +55,7 @@
#define BOARD_ACCEL_NAME "accel"
#define BOARD_ACCEL_IRQ 29 /* PIRQN */
#define BOARD_ACCEL_IRQ_TYPE BOARD_GPIO_INTERRUPT
#define BOARD_ACCEL_IRQ_TYPE BOARD_PIRQ_INTERRUPT
#define BOARD_ACCEL_WAKE_GPIO 45 /* GPIO45 */
#define BOARD_ACCEL_I2C_BUS 2 /* I2C1 */
#define BOARD_ACCEL_I2C_ADDR 0x0e