diff --git a/src/soc/intel/pantherlake/chipset_wcl.cb b/src/soc/intel/pantherlake/chipset_wcl.cb
index ed32d4826d..808d9c7e51 100644
--- a/src/soc/intel/pantherlake/chipset_wcl.cb
+++ b/src/soc/intel/pantherlake/chipset_wcl.cb
@@ -14,6 +14,23 @@ chip soc/intel/pantherlake
 
 	register "tdc_mode[VR_DOMAIN_IA]" = "TDC_IRMS"
 	register "tdc_time_window_ms[VR_DOMAIN_IA]" = "28000"
+	# Set the power state thresholds according to document 830097
+	# Wildcat Lake Platform - Design Guide - Rev 1.5
+	register "ps1_threshold" = "{
+		[VR_DOMAIN_IA] = 20 * 4,
+		[VR_DOMAIN_GT] = 20 * 4,
+		[VR_DOMAIN_SA] = 20 * 4
+	}"
+	register "ps2_threshold" = "{
+		[VR_DOMAIN_IA] = 5 * 4,
+		[VR_DOMAIN_GT] = 5 * 4,
+		[VR_DOMAIN_SA] = 5 * 4
+	}"
+	register "ps3_threshold" = "{
+		[VR_DOMAIN_IA] = 1 * 4,
+		[VR_DOMAIN_GT] = 1 * 4,
+		[VR_DOMAIN_SA] = 1 * 4
+	}"
 
 	# Reduce the size of BasicMemoryTests to speed up the boot time.
 	register "lower_basic_mem_test_size" = "true"