From eb5bdf06b92534b6f66f612297a4ccb69008b4ac Mon Sep 17 00:00:00 2001 From: Sowmya Aralguppe Date: Fri, 27 Feb 2026 14:40:04 +0530 Subject: [PATCH] soc/intel/pantherlake: Add power state thresholds for WCL Configure power state thresholds (PS1, PS2, PS3) according to the platform design specification. These thresholds define current limits at which the voltage regulator domains transition between different power states for optimal power management. Ref=830097_WCL_PDG_SchChk_Rev1p5 BUG=b:None TEST=Build ocelot and verify that the system boots with following VR parameter [SPEW ] (MAILBOX) PS1Threshold = 80 (1/4 Amp) [SPEW ] (MAILBOX) PS2Threshold = 20 (1/4 Amp) [SPEW ] (MAILBOX) PS3Threshold = 4 (1/4 Amp) Change-Id: I8ecb55741901eb997d78a3f1fd09175c3ce31544 Signed-off-by: Sowmya Aralguppe Reviewed-on: https://review.coreboot.org/c/coreboot/+/91454 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- src/soc/intel/pantherlake/chipset_wcl.cb | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/soc/intel/pantherlake/chipset_wcl.cb b/src/soc/intel/pantherlake/chipset_wcl.cb index ed32d4826d..808d9c7e51 100644 --- a/src/soc/intel/pantherlake/chipset_wcl.cb +++ b/src/soc/intel/pantherlake/chipset_wcl.cb @@ -14,6 +14,23 @@ chip soc/intel/pantherlake register "tdc_mode[VR_DOMAIN_IA]" = "TDC_IRMS" register "tdc_time_window_ms[VR_DOMAIN_IA]" = "28000" + # Set the power state thresholds according to document 830097 + # Wildcat Lake Platform - Design Guide - Rev 1.5 + register "ps1_threshold" = "{ + [VR_DOMAIN_IA] = 20 * 4, + [VR_DOMAIN_GT] = 20 * 4, + [VR_DOMAIN_SA] = 20 * 4 + }" + register "ps2_threshold" = "{ + [VR_DOMAIN_IA] = 5 * 4, + [VR_DOMAIN_GT] = 5 * 4, + [VR_DOMAIN_SA] = 5 * 4 + }" + register "ps3_threshold" = "{ + [VR_DOMAIN_IA] = 1 * 4, + [VR_DOMAIN_GT] = 1 * 4, + [VR_DOMAIN_SA] = 1 * 4 + }" # Reduce the size of BasicMemoryTests to speed up the boot time. register "lower_basic_mem_test_size" = "true"