diff --git a/src/soc/qualcomm/x1p42100/Makefile.mk b/src/soc/qualcomm/x1p42100/Makefile.mk
index 1c0d3fe762..36d2578cf5 100644
--- a/src/soc/qualcomm/x1p42100/Makefile.mk
+++ b/src/soc/qualcomm/x1p42100/Makefile.mk
@@ -210,6 +210,13 @@ $(CPUCP_META_CBFS)-type := raw
 $(CPUCP_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
 cbfs-files-y += $(CPUCP_META_CBFS)
 
+################################################################################
+CPUCP_DTBS_FILE := $(X1P42100_BLOB)/cpucp/cpucp_dtbs.elf
+CPUCP_DTBS_CBFS := $(CONFIG_CBFS_PREFIX)/cpucp_dtbs
+$(CPUCP_DTBS_CBFS)-file := $(CPUCP_DTBS_FILE)
+$(CPUCP_DTBS_CBFS)-type := payload
+$(CPUCP_DTBS_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(CPUCP_DTBS_CBFS)
 
 ################################################################################
 SHRM_FILE := $(X1P42100_BLOB)/shrm/shrm.elf
diff --git a/src/soc/qualcomm/x1p42100/cpucp_load_reset.c b/src/soc/qualcomm/x1p42100/cpucp_load_reset.c
index f415bb8555..804c992425 100644
--- a/src/soc/qualcomm/x1p42100/cpucp_load_reset.c
+++ b/src/soc/qualcomm/x1p42100/cpucp_load_reset.c
@@ -1,13 +1,29 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <console/console.h>
+#include <program_loading.h>
 #include <soc/cpucp.h>
-
-void cpucp_prepare(void)
-{
-	/* Placeholder */
-}
+#include <device/mmio.h>
+#include <soc/addressmap.h>
 
 void cpucp_fw_load_reset(void)
 {
-	/* Placeholder */
+	struct prog cpucp_dtbs_prog =
+		PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp_dtbs");
+
+	if (!selfload(&cpucp_dtbs_prog))
+		die("SOC image: CPUCP DTBS load failed");
+
+	printk(BIOS_DEBUG, "SOC image: CPUCP DTBS image loaded successfully.\n");
+
+	struct prog cpucp_fw_prog =
+		PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp");
+
+	if (!selfload(&cpucp_fw_prog))
+		die("SOC image: CPUCP load failed");
+
+	printk(BIOS_DEBUG, "SOC image: CPUCP image loaded successfully.\n");
+
+	write32((void *) HWIO_APSS_CPUCP_CPUCP_LPM_SEQ_WAIT_EVT_CTRL_MASK_ADDR, 0x0);
+	setbits32((void *) HWIO_APSS_CPUCP_CPUCP_SW_WAKEUP_REQ_ADDR, 0x1);
 }
diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
index e0cc910d44..79e2b782e9 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
@@ -15,6 +15,12 @@
 #define NCC0_NCC_CMU_NCC_PLL_CFG	0x199A2010
 #define NCC0_NCC_CMU_NCC_CLK_CFG	0x199A2030
 
+/* CPUCP */
+#define APSS_HM_BASE						0x17000000
+#define APSS_CPUCP_LPM_BFSM_REG_BASE				(APSS_HM_BASE + 0x019d0000)
+#define HWIO_APSS_CPUCP_CPUCP_LPM_SEQ_WAIT_EVT_CTRL_MASK_ADDR	(APSS_CPUCP_LPM_BFSM_REG_BASE + 0x161c)
+#define HWIO_APSS_CPUCP_CPUCP_SW_WAKEUP_REQ_ADDR		(APSS_CPUCP_LPM_BFSM_REG_BASE + 0x1688)
+
 /* X1P42100 QSPI GPIO PINS */
 #define QSPI_CS				GPIO(132)
 #define QSPI_DATA_0			GPIO(128)
diff --git a/src/soc/qualcomm/x1p42100/soc.c b/src/soc/qualcomm/x1p42100/soc.c
index 8066084fee..e8bc4c0996 100644
--- a/src/soc/qualcomm/x1p42100/soc.c
+++ b/src/soc/qualcomm/x1p42100/soc.c
@@ -5,6 +5,7 @@
 #include <soc/mmu_common.h>
 #include <soc/symbols_common.h>
 #include <soc/pcie.h>
+#include <soc/cpucp.h>
 
 static struct device_operations pci_domain_ops = {
 	.read_resources = &qcom_pci_domain_read_resources,
@@ -37,7 +38,7 @@ static void soc_read_resources(struct device *dev)
 
 static void soc_init(struct device *dev)
 {
-	/* placeholder */
+	cpucp_fw_load_reset();
 }
 
 static struct device_operations soc_ops = {