From b0ee0c462051c0f2d03749ecdb8146a61bb69875 Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Thu, 6 Nov 2025 12:52:22 -0800 Subject: [PATCH] soc/intel/pantherlake: Fix IA domain TDC value for PTL_TDC_2 SKU Align the IA domain Thermal Design Current (TDC) value for PTL_TDC_2 with Document #813289 power map revision 2.1. The previous value 23A did not match the updated specification, which now requires 28A. This change ensures that the firmware correctly reflects the hardware power limits for this SKU, preventing potential power delivery issues and improving system stability. Change-Id: I16bb510b8ec2ad1ffdeba20bfe26d0cbad209088 Signed-off-by: Jeremy Compostella Reviewed-on: https://review.coreboot.org/c/coreboot/+/89935 Reviewed-by: Subrata Banik Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/intel/pantherlake/chipset_ptl.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb index e19ca02080..72907656ef 100644 --- a/src/soc/intel/pantherlake/chipset_ptl.cb +++ b/src/soc/intel/pantherlake/chipset_ptl.cb @@ -13,7 +13,7 @@ chip soc/intel/pantherlake [VR_DOMAIN_GT] = 15 * 8 }" register "thermal_design_current[PTL_TDC_2]" = "{ - [VR_DOMAIN_IA] = 23 * 8, + [VR_DOMAIN_IA] = 28 * 8, [VR_DOMAIN_GT] = 23 * 8 }" register "icc_max[PTL_SKU_1]" = "{