From 50ce94d7151c93490d2cc3dd6675561eee6ba374 Mon Sep 17 00:00:00 2001 From: Avi Uday Date: Fri, 6 Mar 2026 10:43:00 +0530 Subject: [PATCH] Revert "soc/intel/pantherlake: Fix DDR5 channel mapping" This reverts commit 835b63980d113232b74b92bc7d1349d3e37d8747, which was causing a boot failure on the ocelot DDR5 RVP. Reverting until further debugging. BUG=b:490040385 Change-Id: I6fa397d26c57c5fb2dd415eaf8ebe5c20476b5f3 Signed-off-by: Avi Uday Reviewed-on: https://review.coreboot.org/c/coreboot/+/91577 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) Reviewed-by: Pranava Y N --- src/soc/intel/pantherlake/meminit.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/pantherlake/meminit.c b/src/soc/intel/pantherlake/meminit.c index f9f8bac8da..eef4adf5f0 100644 --- a/src/soc/intel/pantherlake/meminit.c +++ b/src/soc/intel/pantherlake/meminit.c @@ -35,16 +35,18 @@ static const struct soc_mem_cfg soc_mem_cfg[] = { .num_phys_channels = DDR5_CHANNELS, .phys_to_mrc_map = { [0] = 0, - [1] = 4, + [1] = 1, + [2] = 4, + [3] = 5, }, .md_phy_masks = { /* - * Only channel 0 is populated in case of half-populated - * configuration. + * Physical channels 0 and 1 are populated in case of + * half-populated configurations. */ - .half_channel = BIT(0), - /* In mixed topologies, either channel 0 or 1 can be memory-down. */ - .mixed_topo = BIT(0) | BIT(1), + .half_channel = BIT(0) | BIT(1), + /* In mixed topology, channels 2 and 3 are always memory-down. */ + .mixed_topo = BIT(2) | BIT(3), }, }, [MEM_TYPE_LP5X] = {