coreboot/src/vendorcode/intel
Srinidhi N Kaushik eab9290b5f vendorcode/intel/fsp: Update to include post PRQ UPDs for Tiger Lake
Update FSP headers for Tiger Lake platform generated based on FSP
version 4133 to include post PRQ UPDs.

BUG=b:188452018
BRANCH=none
TEST=build voxel

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I493391294391c1222a1aa5fdb86baad968abf7a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54811
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28 18:25:26 +00:00
..
edk2 treewide: Remove trailing whitespace 2021-02-17 17:30:05 +00:00
fsp vendorcode/intel/fsp: Update to include post PRQ UPDs for Tiger Lake 2021-05-28 18:25:26 +00:00
Kconfig vendorcode/intel: Add edk2-stable202005 support 2020-06-25 11:57:06 +00:00
Makefile.inc vendorcode/intel/Makefile: Add x86_64 support 2021-02-04 10:21:49 +00:00