coreboot/src
Karthikeyan Ramasubramanian fec4db954e soc/amd/cezanne: Configure I2C Pad RX Select through devicetree
Some of the I2C buses are required to operate at different voltage level
compared to other I2C buses eg. I2C bus to Google Security Chip (GSC)
should be at 1.8V level. By default, all the I2C buses are initialized
to operate at 3.3 V. Add support to configure I2C pad RX select through
devicetree and update the concerned devicetree.

BUG=b:188538373
TEST=Build and boot to OS in Guybrush. Ensure that the communication
with GSC is fine. Build Majolica mainboard.

Change-Id: I595a64736fdac0274abffb68c5e521302275b845
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-07 05:18:49 +00:00
..
acpi acpi: drop unused parameter from acpi_soc_fill_bert 2021-06-01 12:49:26 +00:00
arch arch/x86/acpi_bert_storage: change return type of bert_errors_present 2021-05-30 20:16:12 +00:00
commonlib src/intel/xeon_sp: add hardware error support (HEST) 2021-06-04 12:38:32 +00:00
console src: Retype option API to use unsigned integers 2021-05-06 14:48:15 +00:00
cpu cpu/intel/model_206ax/acpi.c: Do not report P_BLK 2021-06-07 04:58:34 +00:00
device device: Consider fw_config probing in is_dev_enabled() 2021-05-24 16:55:39 +00:00
drivers drivers/smmstore: Enable SMMSTORE V2 by default for Tianocore UEFIPAYLOAD 2021-06-07 05:06:23 +00:00
ec ec: Add Star Labs ITE 8987E support 2021-06-04 17:20:56 +00:00
include acpi: drop unused parameter from acpi_soc_fill_bert 2021-06-01 12:49:26 +00:00
lib drivers/pc80/mc146818rtc: Check date and time for sanity 2021-05-30 20:28:14 +00:00
mainboard soc/amd/cezanne: Configure I2C Pad RX Select through devicetree 2021-06-07 05:18:49 +00:00
northbridge nb/intel/x4x/rcven.c: Guard macro parameters 2021-05-28 10:05:37 +00:00
security vboot: Add VB2_CONTEXT_EC_TRUSTED 2021-06-04 18:51:20 +00:00
soc soc/amd/cezanne: Configure I2C Pad RX Select through devicetree 2021-06-07 05:18:49 +00:00
southbridge sb/intel/lynxpoint: Add pch_iobp_exec() function 2021-05-20 16:04:05 +00:00
superio src: Retype option API to use unsigned integers 2021-05-06 14:48:15 +00:00
vendorcode cezanne/psp_verstage: add reset/timer svc 2021-06-07 05:16:20 +00:00
Kconfig option: Allow mainboards to implement the API 2021-05-28 11:37:25 +00:00