Kangheui Won 260f0f93ef cezanne/psp_verstage: add reset/timer svc ... The new cezanne PSP release added support for these svcs. So add those functionality back to cezanne psp_verstage. BUG=b:187906425 Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Id542f5ed0762f582ea966466d67ed938ecb9c1f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>		2021-06-07 05:16:20 +00:00
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amd	cezanne/psp_verstage: add reset/timer svc	2021-06-07 05:16:20 +00:00
cavium	src: use ARRAY_SIZE where possible	2021-02-15 11:30:40 +00:00
eltan	vc/eltan/security/mboot/Kconfig: Add dependency of VBOOT	2021-04-06 07:01:31 +00:00
google	mb/google: Move ECFW_RW setting for non-ChromeEC boards	2021-04-30 06:48:56 +00:00
intel	vendorcode/intel/fsp: Update to include post PRQ UPDs for Tiger Lake	2021-05-28 18:25:26 +00:00
mediatek	vendor/mediatek: Add MT8195 dram initialization code	2021-05-14 04:00:38 +00:00
siemens	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
Makefile.inc	soc/mediatek/mt8192: initialize DRAM using vendor reference code	2021-03-08 03:15:43 +00:00