coreboot/northbridge/amd/k8
Ronald G. Minnich 11c6d0d98d m57sli mostly builds again. The stage0 is too large at 24k.
We need to figure out if we should just grow stage0. My inclination is 
to say 'yes'.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@877 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-01 07:23:05 +00:00
..
coherent_ht.c This finishes the fix to log2. The computed dram size now matches the 2008-09-01 02:44:08 +00:00
common.c This set of changes gets us much farther, in fact, we get into initram. 2008-08-27 05:30:50 +00:00
cpu.c This set of changes gets us much farther, in fact, we get into initram. 2008-08-27 05:30:50 +00:00
domain Forgot to add this one. 2008-09-29 05:14:55 +00:00
domain.c This set of changes adds new nodes to dts that are required, adds 2008-09-18 16:45:46 +00:00
dqs.c m57sli mostly builds again. The stage0 is too large at 24k. 2008-10-01 07:23:05 +00:00
get_sblk_pci1234.c This set of changes gets us much farther, in fact, we get into initram. 2008-08-27 05:30:50 +00:00
incoherent_ht.c This finishes the fix to log2. The computed dram size now matches the 2008-09-01 02:44:08 +00:00
libstage1.c Closer to compiling. Add the fidvid functions. Continue to remove romcc 2008-08-28 17:14:04 +00:00
Makefile More sensible way to conditionally include hypertransport.c 2008-08-24 06:16:03 +00:00
pci The K8 is one example, but there are other devices (e.g. I2C) that also have 2008-09-17 16:36:20 +00:00
pci.c This set of changes adds new nodes to dts that are required, adds 2008-09-18 16:45:46 +00:00
raminit.c m57sli mostly builds again. The stage0 is too large at 24k. 2008-10-01 07:23:05 +00:00
reset_test.c This gets us back to a compiling k8 target. 2008-08-30 03:35:40 +00:00