Set the default MFG MUX OPP (Operating Performance Point) from 0
(mfg_sel) to 1 (mfgpll), as mfgpll is used in normal operation and
mfg_sel is only needed during DVFS transitions. Also enable glitch-free
configuration for mfgpll to improve PLL stability.
BUG=b:399571996
BRANCH=none
TEST=Change GPU DVFS by below commands:
echo 880000000 > /sys/devices/platform/soc/13000000.gpu/devfreq/13000000.gpu/min_freq
echo 880000000 > /sys/devices/platform/soc/13000000.gpu/devfreq/13000000.gpu/max_freq
And then check PLL and MUX register values are correct.
Signed-off-by: Irving-CH lin <irving-ch.lin@mediatek.corp-partner.google.com>
Change-Id: I285cc5f07facbb23a448151ceb6c1d037753432c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88090
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
f941b51e0e