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soc/mediatek/mt8189: Correct MFG MUX OPP init setting

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Set the default MFG MUX OPP (Operating Performance Point) from 0
(mfg_sel) to 1 (mfgpll), as mfgpll is used in normal operation and
mfg_sel is only needed during DVFS transitions. Also enable glitch-free
configuration for mfgpll to improve PLL stability.

BUG=b:399571996
BRANCH=none
TEST=Change GPU DVFS by below commands:
echo 880000000 > /sys/devices/platform/soc/13000000.gpu/devfreq/13000000.gpu/min_freq
echo 880000000 > /sys/devices/platform/soc/13000000.gpu/devfreq/13000000.gpu/max_freq
And then check PLL and MUX register values are correct.

Signed-off-by: Irving-CH lin <irving-ch.lin@mediatek.corp-partner.google.com>
Change-Id: I285cc5f07facbb23a448151ceb6c1d037753432c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88090
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Irving-CH Lin 2025-06-11 11:58:15 +08:00 • committed by Yidi Lin
commit f941b51e0e
1 changed files with 2 additions and 1 deletions
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3
src/soc/mediatek/mt8189/pll.c
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@ -559,6 +559,7 @@ void mt_pll_init(void)
write32(&mtk_apmixed->apll1_tuner_con0, 0x6F28BD4D);
write32(&mtk_apmixed->apll2_tuner_con0, 0x78FD5266);
setbits32(&mtk_apmixed->emipll_con[0], BIT(8));
setbits32(&mtk_apmixed->mfgpll_con[0], BIT(8));
/* PLL all enable */
write32(&mtk_apmixed->pllen_all_set, 0x0007FFFC);
@ -622,7 +623,7 @@ void mt_pll_post_init(void)
/* TOPCKGEN CG Clear */
write32(&mtk_topckgen->clk_misc_cfg_3.clr, 0x00010000);
write32(&mtk_topckgen->clk_misc_cfg_3.set, 0xDF3CFCFF);
write32(&mtk_topckgen->clk_misc_cfg_3.set, 0xDF3DFCFF);
/* INFRACFG_AO CG Clear */
write32(&mtk_infracfg_ao->infracfg_ao_module_cg_0_clr, 0x10000000);
write32(&mtk_infracfg_ao->infracfg_ao_module_cg_1_clr, 0x21000000);