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coreboot/src/arch/arm
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Jimmy Zhang c3d585bdfc arm: lpae: Set XN and PXN bits for noncacheable regions 
Add XN/PXN bits to prevent cpu from fetching speculative instructions
on noncacheable region.

BUG=chrome-os-partner:28568
BRANCH=nyan
TEST=Build and run reboot tests on nyan_big

Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>

Change-Id: I0cd2ad5a47a467ef609d30d42cd300b5ca45b77b
Reviewed-on: https://chromium-review.googlesource.com/203447
Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-06-12 04:31:52 +00:00
..
armv4 coreboot: Introduce stage-specific architecture for coreboot 2014-05-09 04:41:47 +00:00
armv7 arm: lpae: Set XN and PXN bits for noncacheable regions 2014-06-12 04:31:52 +00:00
include ipq8064: storm: re-arrange bootblock initialization 2014-05-02 00:42:07 +00:00
libgcc coreboot: Introduce stage-specific architecture for coreboot 2014-05-09 04:41:47 +00:00
asmlib.h arm: Update mem* functions to newer versions 2014-01-14 03:29:44 +00:00
boot.c libpayload: arm: Pass the coreboot table location to the payload. 2014-02-11 05:30:59 +00:00
bootblock.ld arm: Add support for a preram_cbmem_console symbol. 2014-04-10 04:19:04 +00:00
cpu.c
div0.c
eabi_compat.c
early_console.c console: Make more consoles (including cbmem) work in the bootblock. 2014-04-10 06:05:06 +00:00
id.S
Kconfig coreboot: Introduce stage-specific architecture for coreboot 2014-05-09 04:41:47 +00:00
Makefile.inc coreboot: Introduce stage-specific architecture for coreboot 2014-05-09 04:41:47 +00:00
memcpy.S arm: Put assembly functions into separate sections 2014-01-29 21:33:41 +00:00
memmove.S arm: Put assembly functions into separate sections 2014-01-29 21:33:41 +00:00
memset.S arm: Put assembly functions into separate sections 2014-01-29 21:33:41 +00:00
ramstage.ld coreboot: Rename coreboot_ram stage to ramstage 2014-05-07 23:30:23 +00:00
romstage.ld coreboot: Rename coreboot_ram stage to ramstage 2014-05-07 23:30:23 +00:00
stages.c arm: Redesign, clarify and clean up cache related code 2014-01-29 21:33:35 +00:00
tables.c
timestamp.c