This commit introduces PCI device details specific to Wildcat Lake
within the Panther Lake ACPI code, using conditional compilation
to differentiate configurations.
Key changes:
- Create separate ASL files for Panther Lake (`ptl_pcie.asl`) and
Wildcat Lake (`wcl_pcie.asl`) PCIe port configurations.
- Introduce conditional compilation to include Panther Lake or
Wildcat Lake ASL files.
- Wildcat Lake-specific changes compared to Panther Lake:
- Remove following
- PCIe RP : 00:1c.4 to 00:1c.7
: 00:06.2 & 00:06.3
References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
BUG=b:394208231
TEST=Build Ocelot and Fatcat and verify it compiles without any error.
Change-Id: I7f6c4f80a811c596824734d749b8d1c4864ccb9b
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88109
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
f3f9c0bd8e