coreboot/src
Aaron Durbin f3803cbe6a baytrail: use common code for iosf accessors
The same sequence is used regardless of the port
being read or written. Therefore, use the same
implementation for reading or writing to a port.

BUG=None
BRANCH=None
TEST=Built and booted through depthcharge. Dev and recovery
     screens still work. Nothing bizarre in console output.

Change-Id: I1a64b54b50472fa7d601e199653eb4a76accf910
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175441
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2013-11-01 18:12:06 +00:00
..
arch nyan: tegra124: Enable I, D and L2 caches in romstage. 2013-10-29 02:59:07 +00:00
console ARM: Generalize armv7 as arm. 2013-10-02 09:18:44 +00:00
cpu x86: Add SMM helper functions to MP infrastructure 2013-10-23 04:08:19 +00:00
device ARM: Generalize armv7 as arm. 2013-10-02 09:18:44 +00:00
drivers drivers/gma: remove unused code 2013-10-11 20:36:54 +00:00
ec chrome ec: Fix ASL to use IO() instead of FixedIO() 2013-10-30 01:02:21 +00:00
include rmodule: consolidate rmodule stage loading 2013-10-24 18:06:13 +00:00
lib cbfs: Check return value of map() for error 2013-10-29 19:14:52 +00:00
mainboard samus: GPIO updates for Proto1b 2013-10-31 20:52:03 +00:00
northbridge haswell: Report x32 memory as "x8 or x32" 2013-10-23 21:27:19 +00:00
soc baytrail: use common code for iosf accessors 2013-11-01 18:12:06 +00:00
southbridge lynxpoint: Allow to always route USB3 ports to XHCI 2013-10-22 21:42:00 +00:00
superio Drop prototype guarding for romcc 2013-05-10 11:55:20 -07:00
vendorcode rmodule: consolidate rmodule stage loading 2013-10-24 18:06:13 +00:00
Kconfig x86: add HAVE_REFCODE_BLOB option 2013-10-24 18:06:07 +00:00