A need arose to perform power and performance analysis on various SoC
SKUs with Fast VMode enabled, which the current chipset data structure
does not allow.
This commit refactors the configuration of Fast VMode I_TRIP thresholds
for Voltage Regulator (VR) domains across different power limit
configurations in Pantherlake SoCs. Previously, the I_TRIP threshold
values were statically set for each VR domain, but now they are defined
within a two-dimensional array that considers various power limit
scenarios.
This commit adds the I_TRIP values for different Power Limit SKUs
currently operated on Fatcat devices.
As part of this commit, the following two changes are being undone
because the previous code structure is now incompatible and lacks
purpose:
- commit 4b765fdd98 ("mb/google/fatcat: Disable EnableFastVmode on
Panther Lake H SoC")
- commit 5d7e2b4c0c ("mb/google/fatcat: Disable VR settings on Panther
Lake H SoC")
Change-Id: Iff21a9b0b230e08b99e032400cbe0021b8a4af43
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
e58883aace