coreboot/src
Walter Sonius d5bce8c420 mb/hp: Add HP 260 G1 DM Business PC (Haswell)
This HP desktop comes in 4 different CPU variants. This port was made
using the Pentium 3558U @ 1.70GHz variant with 2*4GB DDR3L SODIMM RAM
modules with a single SATA adapter cable. Other variants may come with
an M2.SSD slot which may need other devicetree.cb PCIe / SATA edits!

Model: HP 260 G1 DM Business PC
Regulatory Model: TPC-1011-DM
Product No.: N9F00EA#ABH, 260G1eD/G3558U/500h/4X/50f NL
Mainboard: E131920, 791401-002

Pure autoport (initial commit) doesn't boot, further patches bring up
general Haswell fixes, vendor/product naming corrected, RAM SPD MAP
slot detection, (m)PCIe fixes enabling onboard LAN and mini PCIe slot
and some NPCD379 code from other HP desktops make most superio related
functions work for this PC.

Flash instructions:
After setting the FDO jumper on the motherboard the whole ROM can be
dumped, however writing is locked for some part of the BIOS region.
An external flasher ch341a_spi (3.3v mod) was used with a SOIC 8 pomona
probe to flash the MX25L6406E in situ without any issues. Only the
power of the USB programmer was used, and the board's main PSU was
disconnected during flash!

Tested:
 - coreboot 25.06-77-g812d0e2f626d as base
 - EDK2 (MrChromebox/2502)
 - SeaBIOS 1.16.3
 - SystemAgent mrc.bin (haswell/peppy)
 - libgfxinit textmode (SeaBIOS) / framebuffer (EDK2)
 - DP / DP++ (HDMI) & VGA all available during POST, BOOT and OS
 - Pentium 3558U
 - RAM single 4GB and dual slot 8GB total with 1.35V DDR3L SODIMMS
	4GB DDR3-1600 - SK Hynix HMT451S6BFR8A-PB (2016-W01)
	    HMT451S6BFR8A-PB NO AA 1601
	    1Rx8 PC3L-12800S-11-13-B4
	4GB DDR3 1600 - Kingston 9905469-143.A00LF (2016-W05)
	    KTH-X3CL/4G
	    1.35V
	    BPMK0831621
	    9905469-143.A00LF
	    0000007258426-PW005291
 - Fedora MATE 42 (Kernel 6.14)
 - KDE NEON 6.4 (Kernel 6.11)
 - Audio Outputs HDMI, Headphone, Lineout & Speaker (left&right chan.)
 - USB2/3 all ports
 - Realtek onboard Gb LAN
 - miniPCIe slot + its embedded USB (Intel Wireless AC3160HMW+BT)
 - SATA port using the original flatcable adapter
 - PowerButton (Poweron/Poweroff/Wake)
 - LEDs HDD & POWER (both off during suspend)
 - Shutdown/Reboot/Suspend
 - Strip down the Intel ME/TXE firmware (make menuconfig)
 - Disabling ME HECI (manually disable in devicetree.cb)
 - flashrom -p internal -c "MX25L6406E/MX25L6408E" (read & write)

Not tested:
 - Broadwell mrc.bin
 - Front Microphone Port
 - USBDEBUG
 - VBIOS

Not working:
 - FAN control its either full OFF or full ON see instruction!
 - Wake on LAN
 - Ethernet is detected as PCIe slot connected instead of onboard
 - Disable Intel ME PCI interface (make menuconfig)
 - Windows 10/11 USB detection/hotplug issues (all USB ports)
 - Haswell NRI (posts & boots but will shutdown in less than a minute)

FAN instructions:
If the superio HWM (devicetree.cb node pnp 2e.8) is set to on, the FAN
will turn OFF during post and stays OFF. If the superio HWM pnp 2e.8 is
set to off the FAN will stay ON and will rampup after post in roughly a
minute to its maximum RPM and will stay that way (current default)!

The data.vbt blob was extracted using debugfs from the OEM firmware
v2.19 which enables all video outputs Displayport / DP++ (HDMI) and VGA.

Theoretically like the "compaq_8200_elite_sff" it should be possible
to flash internally using a 2 step flash procedure using a minimized ME
a small SeaBIOS based coreboot and a temporary flash layout inside the
writeable BIOS region.

Change-Id: Ifedd9f700e5f3875d3577fa56225d9d49d622b47
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88326
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-07-10 16:47:34 +00:00
..
acpi drivers/crb/tpm: Add new method to retrieve base address 2025-07-02 16:15:09 +00:00
arch arch/x86/postcar_loader: Add comment line for reloc_params assignment 2025-07-07 14:30:58 +00:00
commonlib commonlib: Add pvmfw related timestamps 2025-07-08 09:22:21 +00:00
console console/i2c_smbus: Allow to send data w/o register offset 2024-07-11 00:06:22 +00:00
cpu cpu/intel/haswell: Export PCODE mailbox functions 2025-05-27 15:07:25 +00:00
device device/device_util.c: Complete function documentation 2025-06-15 12:55:59 +00:00
drivers drivers/emu/qemu: Add a comment about fw_cfg assumptions 2025-07-08 16:18:17 +00:00
ec mb/google/brox: Enable support for Realtek EC 2025-06-20 17:48:07 +00:00
include soc/intel/pantherlake: Add new MCH ID for Wildcat Lake 2025-07-04 13:17:15 +00:00
lib lib/cbfs: Ensure cache buffer alignment in ramstage 2025-07-09 14:10:16 +00:00
mainboard mb/hp: Add HP 260 G1 DM Business PC (Haswell) 2025-07-10 16:47:34 +00:00
northbridge Haswell NRI: Implement COMP offset optimisation 2025-07-04 13:17:47 +00:00
sbom sbom: Fix build with merged bootblock and romstage 2025-07-07 14:29:29 +00:00
security security/vboot: Back up CMOS data later boot phase 2025-06-05 13:36:19 +00:00
soc soc/mediatek/mt8196: Remove redundant bootblock.c from Makefile.mk 2025-07-09 04:55:47 +00:00
southbridge sb/intel/lynxpoint: Add CFR objects for existing options 2025-04-25 14:24:47 +00:00
superio src/superio/nuvoton: Add HWM initialization code 2025-06-11 13:31:25 +00:00
vendorcode vc/intel/fsp2_0/twinlake: Update FSP headers 2025-07-04 13:17:59 +00:00
Kconfig security/vboot: Back up CMOS data later boot phase 2025-06-05 13:36:19 +00:00