Jimmy Zhang d08c0f7c5e nyan*: debug: Add sor registers dump function ... Dump all SOR registers for debug purpose. By default, this function is not being built in. BRANCH=none BUG=chrome-os-partner:27413 TEST=build nyan and nyan_big. Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Change-Id: I7f44709b8572b9eac33c2193b92a65bf2b22aa76 Reviewed-on: https://chromium-review.googlesource.com/194738 Reviewed-by: Tom Warren <twarren@nvidia.com> Commit-Queue: Tom Warren <twarren@nvidia.com> Tested-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>		2014-04-17 16:43:27 +00:00
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arch	console: Make more consoles (including cbmem) work in the bootblock.	2014-04-10 06:05:06 +00:00
console	Copy u-boot sources as is and modify the tree to still build	2014-04-11 00:04:09 +00:00
cpu	x86: Set BOOT_MEDIA_SPI_BUS	2014-04-15 05:41:46 +00:00
device	Remove stale char[] initialization causing unaligned memory access	2014-03-14 03:44:47 +00:00
drivers	spi: Add W25Q32DW	2014-04-16 08:36:01 +00:00
ec	i2c: Replace the i2c API.	2014-04-10 06:05:01 +00:00
include	i2c: Replace the i2c API.	2014-04-10 06:05:01 +00:00
lib	console: Make more consoles (including cbmem) work in the bootblock.	2014-04-10 06:05:06 +00:00
mainboard	tegra124: Setup clock PLLD by approximating display panel pixel clock.	2014-04-15 05:42:20 +00:00
northbridge	spi: Remove unused parameters from spi_flash_probe and setup_spi_slave.	2014-04-01 23:21:22 +00:00
soc	nyan*: debug: Add sor registers dump function	2014-04-17 16:43:27 +00:00
southbridge	x86: Initialize SPI controller explicitly during PCH init	2014-04-17 16:42:37 +00:00
superio	pnp: Allow setting of misc register 0xf4 in device tree	2013-12-20 00:37:38 +00:00
vendorcode	tegra124: Skip display init when vboot says we don't need it.	2014-04-03 22:41:54 +00:00
Kconfig	armv8: add support for armv8 cpu	2014-01-07 02:48:47 +00:00