x86: Initialize SPI controller explicitly during PCH init

This ensures that SPI is ready when eventlog code is used.

x86 platforms which use eventlog invoke elog_clear() in GSMI and
elog_add_event_raw() when deciding the boot path based on ME status.
For the SMM case spi_init() is called during the finalize stage in
SMM setup. For the boot path case we can call spi_init() at the
beginning of BS_DEV_INIT and it will be ready to use when the boot
path is determined from the ME status.

BUG=none
BRANCH=none
TEST=tested on Link (bd82x6x), Beltino (Lynxpoint), and Rambi
(Baytrail) with follow-up patch
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Id3aef0fc7d4df5aaa3c1c2c2383b339430e7a6a1
Reviewed-on: https://chromium-review.googlesource.com/194525
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>

src/soc/intel/baytrail/spi.c

@@ -24,6 +24,7 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include <string.h>
+#include <bootstate.h>
 #include <delay.h>
 #include <arch/io.h>
 #include <console/console.h>
@@ -316,6 +317,16 @@ void spi_init(void)
 	ich_set_bbar(0);
 }
 
+
+static void spi_init_cb(void *unused)
+{
+	spi_init();
+}
+
+BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = {
+        BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL),
+};
+
 int spi_claim_bus(struct spi_slave *slave)
 {
 	/* Handled by ICH automatically. */

src/southbridge/intel/bd82x6x/spi.c

@@ -24,6 +24,7 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include <string.h>
+#include <bootstate.h>
 #include <delay.h>
 #include <arch/io.h>
 #include <console/console.h>
@@ -407,6 +408,15 @@ void spi_init(void)
 	pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1);
 }
 
+static void spi_init_cb(void *unused)
+{
+	spi_init();
+}
+
+BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = {
+        BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL),
+};
+
 int spi_claim_bus(struct spi_slave *slave)
 {
 	/* Handled by ICH automatically. */

src/southbridge/intel/lynxpoint/spi.c

@@ -24,6 +24,7 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include <string.h>
+#include <bootstate.h>
 #include <delay.h>
 #include <arch/io.h>
 #include <console/console.h>
@@ -319,6 +320,15 @@ void spi_init(void)
 	pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1);
 }
 
+static void spi_init_cb(void *unused)
+{
+	spi_init();
+}
+
+BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = {
+        BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL),
+};
+
 int spi_claim_bus(struct spi_slave *slave)
 {
 	/* Handled by ICH automatically. */