Felix Held cdbfa6e637 soc/amd/common/block/include/espi: rename IO/MMIO base/size registers ... This aligns the register names more with the PPR. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4e7dc8dfc0fa5e86b9d4425f2496be86e039b686 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>		2022-02-11 14:18:44 +00:00
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cezanne	soc/amd/cezanne: Disable CONSOLE_CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTS	2022-02-08 16:19:11 +00:00
common	soc/amd/common/block/include/espi: rename IO/MMIO base/size registers	2022-02-11 14:18:44 +00:00
picasso	soc/amd/picasso/psp_verstage: Implement get_uart_base	2022-02-08 16:18:21 +00:00
sabrina	soc/amd/sabrina/Kconfig: remove SOC_AMD_COMMON_BLOCK_PCI_MMCONF TODO	2022-02-08 17:09:18 +00:00
stoneyridge	treewide: Remove "ERROR: "/"WARN: " prefixes from log messages	2022-02-07 23:29:09 +00:00
Kconfig