Duncan Laurie cd47228ecd baytrail: Enable Turbo/Burst and set some magic MSRs ... As far as I can tell turbo enabling behaves like it did on haswell so use the standard code. There are also some magic values to set in some magic MSRs related to turbo and package power so they report correctly. The L2 cache shrink is enabled and a threshold is set that makes both dual and quad core happy. C1E is disabled to match the reference code. BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: Ic6d4283d480a44d85a9b96571baf83928615665c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175743 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org>		2013-11-11 19:37:36 +00:00
..
arch	nyan: tegra124: Enable I, D and L2 caches in romstage.	2013-10-29 02:59:07 +00:00
console	ARM: Generalize armv7 as arm.	2013-10-02 09:18:44 +00:00
cpu	x86: Add SMM helper functions to MP infrastructure	2013-10-23 04:08:19 +00:00
device	pnp: Allow setting of misc register 0xfa in device tree	2013-11-08 00:52:45 +00:00
drivers	drivers/gma: remove unused code	2013-10-11 20:36:54 +00:00
ec	chrome ec: Fix ASL to use IO() instead of FixedIO()	2013-10-30 01:02:21 +00:00
include	regscript: Add support for MSR type	2013-11-11 19:37:32 +00:00
lib	regscript: Add support for MSR type	2013-11-11 19:37:32 +00:00
mainboard	rambi: include the EC devices normally on superio	2013-11-08 04:47:09 +00:00
northbridge	haswell: Report x32 memory as "x8 or x32"	2013-10-23 21:27:19 +00:00
soc	baytrail: Enable Turbo/Burst and set some magic MSRs	2013-11-11 19:37:36 +00:00
southbridge	lynxpoint: Allow to always route USB3 ports to XHCI	2013-10-22 21:42:00 +00:00
superio	pnp: Allow setting of misc register 0xfa in device tree	2013-11-08 00:52:45 +00:00
vendorcode	rmodule: consolidate rmodule stage loading	2013-10-24 18:06:13 +00:00
Kconfig	Fix the reg_script stuff to not be used in ARM builds and not break them.	2013-11-02 01:07:13 +00:00