coreboot/src/southbridge/intel
Furquan Shaikh 7adf4b8fdb UPSTREAM: drivers/spi: Re-factor spi_crop_chunk
spi_crop_chunk is a property of the SPI controller since it depends
upon the maximum transfer size that is supported by the
controller. Also, it is possible to implement this within spi-generic
layer by obtaining following parameters from the controller:

1. max_xfer_size: Maximum transfer size supported by the controller
(Size of 0 indicates invalid size, and unlimited transfer size is
indicated by UINT32_MAX.)

2. deduct_cmd_len: Whether cmd_len needs to be deducted from the
max_xfer_size to determine max data size that can be
transferred. (This is used by the amd boards.)

BUG=none
BRANCH=none
TEST=none

Change-Id: Iae7e196ab1e3fc1a665a4d27e722b920e78e8fd8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: de705fa1f4
Original-Change-Id: I81c199413f879c664682088e93bfa3f91c6a46e5
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19386
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Tested-by: coreboot org <coreboot.org@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/498323
2017-05-07 16:25:58 -07:00
..
bd82x6x UPSTREAM: sb/intel/bd82x6x/bootblock: Use register name 2017-05-07 16:25:52 -07:00
common UPSTREAM: drivers/spi: Re-factor spi_crop_chunk 2017-05-07 16:25:58 -07:00
fsp_bd82x6x UPSTREAM: nb/intel/fsp_sandybridge/gma: Set up OpRegion in nb code 2017-05-02 20:24:07 -07:00
fsp_i89xx UPSTREAM: nb/intel/fsp_sandybridge/gma: Set up OpRegion in nb code 2017-05-02 20:24:07 -07:00
fsp_rangeley UPSTREAM: drivers/spi: Re-factor spi_crop_chunk 2017-05-07 16:25:58 -07:00
i3100 UPSTREAM: sb/intel/i3100/lpc.c: Use tab for indents 2016-11-30 02:53:37 -08:00
i82371eb UPSTREAM: southbridge/intel/i82371eb: transition away from device_t 2016-09-13 22:19:42 -07:00
i82801ax UPSTREAM: southbridge/intel/i82801ax: transition away from device_t 2016-09-13 22:19:44 -07:00
i82801bx
i82801dx UPSTREAM: intel/i82801dx: Support 2MiB FWH part 2017-01-13 15:22:00 -08:00
i82801ex UPSTREAM: src/southbridge: Code formating 2016-09-04 19:36:57 -07:00
i82801gx UPSTREAM: i82801gx: Enable PCI-to-PCI bridge 2017-04-28 22:25:27 -07:00
i82801ix UPSTREAM: intel/i82801ix: Add HAVE_INTEL_FIRMWARE 2016-12-19 09:55:21 -08:00
i82870 UPSTREAM: src/southbridge: Code formating 2016-09-04 19:36:57 -07:00
ibexpeak UPSTREAM: nb/intel/nehalem/gma: Set up OpRegion in nb code 2017-05-02 20:24:08 -07:00
lynxpoint UPSTREAM: lynxpoint bd82x6x: Enable PCI-to-PCI bridge 2017-02-27 14:07:49 -08:00