coreboot/src/southbridge
Kyösti Mälkki 5413dfd0f4 UPSTREAM: AGESA: Fix UMA calculations
Vendorcode decides already in AMD_INIT_POST the exact location
of UMA memory. To meet alignment requirements, it will extend
uma_memory_size. We cannot calculate base from size and TOP_MEM1,
but need to calculate size from base and TOP_MEM1 instead.

Also allows selection of UmaMode==UMA_SPECIFIED to manually set
amount of memory reserved for framebuffer.

BUG=none
BRANCH=none
TEST=none

Change-Id: Ie72f645e841d758ad4a275c39111c3a785ddd883
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 61be3603f4
Original-Change-Id: I2514c70a331c7fbf0056f22bf64f19c9374754c0
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19328
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/508778
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2017-05-18 18:07:13 -07:00
..
amd UPSTREAM: AGESA: Fix UMA calculations 2017-05-18 18:07:13 -07:00
broadcom UPSTREAM: amdfam10: Perform major include ".c" cleanup 2017-01-05 11:01:40 -08:00
intel UPSTREAM: drivers/spi: Re-factor spi_crop_chunk 2017-05-07 16:25:58 -07:00
nvidia UPSTREAM: sb/nvidia/mcp55: Link early_ctrl.c 2017-04-28 22:25:37 -07:00
ricoh/rl5c476 UPSTREAM: sb/ricoh/rl5c476/rl5c476.c: Use tab for indents 2016-11-30 02:53:26 -08:00
sis/sis966 UPSTREAM: PCI ops: Remove conflicting duplicate declarations 2016-12-08 12:31:07 -08:00
ti southbridge/ti: Update license headers 2016-04-13 17:36:00 +02:00
via UPSTREAM: nb/amd/amdk8: Link raminit_f.c 2017-04-28 22:25:26 -07:00