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UPSTREAM: lynxpoint bd82x6x: Enable PCI-to-PCI bridge

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Once the PCI command register is written the bridge forwards
future IO and memory regions, as programmed in the respective base
and limit registers, to the secondary PCI bus.

It was previously argumented this is copy-paste and never known
to be required for these more recent platforms:
   https://review.coreboot.org/#/c/2706/

BUG=none
BRANCH=none
TEST=none

Change-Id: If3fb9ee922b6f202a5a9d5e654066b50507b0f01
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 57d4c30e22
Original-Change-Id: Ic8911500a30bc83587af8d4b393b66783fa52e18
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18330
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446385
This commit is contained in:
Kyösti Mälkki 2017-02-11 17:31:25 +02:00 • committed by chrome-bot
commit 0e7729bcb7
2 changed files with 0 additions and 14 deletions
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9
src/southbridge/intel/bd82x6x/pci.c
View file

@ -59,7 +59,6 @@ static void pci_init(struct device *dev)
pci_write_config16(dev, SECSTS, reg16);
}
#undef PCI_BRIDGE_UPDATE_COMMAND
static void ich_pci_dev_enable_resources(struct device *dev)
{
const struct pci_operations *ops;
@ -79,16 +78,8 @@ static void ich_pci_dev_enable_resources(struct device *dev)
command = pci_read_config16(dev, PCI_COMMAND);
command |= dev->command;
#ifdef PCI_BRIDGE_UPDATE_COMMAND
/* If we write to PCI_COMMAND, on some systems
* this will cause the ROM and APICs not being visible
* anymore.
*/
printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
pci_write_config16(dev, PCI_COMMAND, command);
#else
printk(BIOS_DEBUG, "%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
#endif
}
static void ich_pci_bus_enable_resources(struct device *dev)

5
src/southbridge/intel/lynxpoint/pci.c
View file

@ -59,7 +59,6 @@ static void pci_init(struct device *dev)
pci_write_config16(dev, SECSTS, reg16);
}
#undef PCI_BRIDGE_UPDATE_COMMAND
static void ich_pci_dev_enable_resources(struct device *dev)
{
const struct pci_operations *ops;
@ -79,16 +78,12 @@ static void ich_pci_dev_enable_resources(struct device *dev)
command = pci_read_config16(dev, PCI_COMMAND);
command |= dev->command;
#ifdef PCI_BRIDGE_UPDATE_COMMAND
/* If we write to PCI_COMMAND, on some systems
* this will cause the ROM and APICs not being visible
* anymore.
*/
printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
pci_write_config16(dev, PCI_COMMAND, command);
#else
printk(BIOS_DEBUG, "%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
#endif
}
static void ich_pci_bus_enable_resources(struct device *dev)