Jincheng Li ced4c09359 soc/intel/xeon_sp/gnr: Implement get_mmio_high_base_size ... Report above 4G MMIO base and size to coreboot so that coreboot could correctly set MTRR coverage for the whole region instead of only covering PCI driver used parts, where much fragmentation was introduced. TESTED=Build and boot on intel/avenuecity CRB, check MTRR usage: [DEBUG] 0x0000000080000000: PHYBASE0: Address = 0x0000000080000000, UC [DEBUG] 0x000fffff80000800: PHYMASK0: Length = 0x0000000080000000, Valid [DEBUG] 0x00001e0000000000: PHYBASE1: Address = 0x00001e0000000000, UC [DEBUG] 0x000fff0000000800: PHYMASK1: Length = 0x0000010000000000, Valid [DEBUG] 0x00001f0000000000: PHYBASE2: Address = 0x00001f0000000000, UC [DEBUG] 0x000fffc000000800: PHYMASK2: Length = 0x0000004000000000, Valid [DEBUG] 0x0000000000000000: PHYBASE3 [DEBUG] 0x0000000000000000: PHYMASK3: Disabled Change-Id: I61a7e96b3e7566d6a2c14951e7eb4f0be98c13e5 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88279 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2025-07-18 03:38:34 +00:00
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amd	soc/amd/glinda: Don't let OS put debug UART into D3	2025-06-04 18:00:06 +00:00
cavium
example/min86
ibm/power9
intel	soc/intel/xeon_sp/gnr: Implement get_mmio_high_base_size	2025-07-18 03:38:34 +00:00
mediatek	soc/mediatek/mt8189: Specify MTKLIB_PATH for building BL31	2025-07-17 13:36:17 +00:00
nvidia
qualcomm	soc/qualcomm/x1p42100: Update boot critical firmware memory layout	2025-07-15 07:31:39 +00:00
rockchip
samsung	samsung/exynos5250: Replace 'unsigned long int' by 'unsigned long'	2025-01-15 08:32:16 +00:00
sifive
ti
ucb/riscv	soc/riscv/ucb: Switch to FDT parsing to get memory size	2025-02-26 17:11:09 +00:00
xilinx	soc/xilinx/zynq7000: Initial Xilinx Zynq 7000 SoC bringup	2025-01-23 00:41:01 +00:00