coreboot/src/soc
Hari L 8449a15aed soc/qualcomm/x1p42100: Reduce USB OTG state enable timeout to 20ms
Reduce maximum timeout from 100ms to 20ms for OTG Enablement polling
for USB Type-C.

Avoid OTG enablement polling when in sink mode

BUG=b:455551151
TEST: Verify USB3.0 (SS) works for C0/C1 on Google/Bluey.

Background:
During USB Type-C port initialization, the OTG (On-The-Go) status must
be verified when the port operates in source mode to ensure proper VBUS
power delivery. The previous implementation polled the OTG status
register with a 100ms timeout on all ports regardless of their role.

Previous Implementation Issues:
1. Overly conservative timeout: The 100ms maximum wait significantly
   exceeded actual requirements, as OTG enablement consistently
   completes in approximately 14ms under normal conditions
2. Inefficient polling logic: OTG status was polled even when ports
   operated in sink mode, where OTG functionality is irrelevant since
   the port receives rather than provides power

Improvements:
1. Timeout reduction: Decreased maximum polling duration from 100ms to
   20ms, maintaining adequate margin (>40% headroom) while reducing boot
   time by up to 80ms per sink-mode port
2. Mode-aware polling: Added logic to detect port role and skip OTG
   status polling entirely for sink-mode ports, as demonstrated by the
   "Primary in SNK mode - skipping OTG status read" log entry

The changes maintain full USB3.0 SuperSpeed functionality while
improving initialization efficiency. The 20ms timeout remains
sufficiently conservative to accommodate normal timing variations.

Debug logs:
[DEBUG]  QMP PHY SS0 initialized and locked in 1671us,
	phy_status: 0x86868686
[INFO ]  Enabling Primary VBUS SuperSpeed
[INFO ]  Primary in SNK mode - skipping OTG status read
[INFO ]  Primary Type-C Status:
[INFO ]    Misc Status (0x2B0B): 0x1a
[INFO ]    Src Status (0x2B08): 0x00
[INFO ]    Mode Config (0x2B44): 0x00
[INFO ]    Interrupt En Cfg 1 (0x2B5E): 0xff
[INFO ]    State Machine Status (0x2B09): 0x02
[DEBUG]  USB HS PHY initialized for index 3
[DEBUG]  QMP-1x16 USB4 DP PHY SS1 init
[DEBUG]  QMP PHY SS1 initialized and locked in 1671us,
	phy_status: 0x86868686
[INFO ]  Enabling Secondary VBUS SuperSpeed
[INFO ]  Secondary in SRC mode - OTG Status: 0x02, State: 0x02
	(OTG Enabled) - Time: 14 ms
[INFO ]  Secondary Type-C Status:
[INFO ]    Misc Status (0x2B0B): 0x4b
[INFO ]    Src Status (0x2B08): 0x08
[INFO ]    Mode Config (0x2B44): 0x00
[INFO ]    Interrupt En Cfg 1 (0x2B5E): 0xff
[INFO ]    State Machine Status (0x2B09): 0xa6

confirmed that there are no otg polling for sink mode and
polling timeout is reduced to max of 20ms.

Change-Id: I7467248185c9d0526816ac62e1e1a1496440fddc
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2025-11-06 13:17:24 +00:00
..
amd soc/amd/turin_poc: Add Turin SoC structure as a copy of genoa_poc 2025-10-24 21:38:41 +00:00
cavium soc/cavium: Fix non matching types 2024-08-30 07:34:47 +00:00
example/min86
ibm/power9 soc/power9/rom_media.c: find CBFS in PNOR 2025-08-28 20:14:01 +00:00
intel soc/intel/pantherlake/romstage: Configure VGA mode 12 planar buffer 2025-11-05 14:10:25 +00:00
mediatek soc/mediatek/mt8189: Require libbl31.a to exist 2025-11-05 03:52:43 +00:00
nvidia arch/arm: Add a few ARM targets as supported by CLANG 2024-08-23 10:40:01 +00:00
qualcomm soc/qualcomm/x1p42100: Reduce USB OTG state enable timeout to 20ms 2025-11-06 13:17:24 +00:00
rockchip arch/arm: Add a few ARM targets as supported by CLANG 2024-08-23 10:40:01 +00:00
samsung samsung/exynos5250: Replace 'unsigned long int' by 'unsigned long' 2025-01-15 08:32:16 +00:00
sifive tree: Remove unused <assert.h> 2024-11-19 00:40:04 +00:00
ti soc/ti/am335x: Remove superfluous formats 2024-08-02 14:45:13 +00:00
ucb/riscv soc/riscv/ucb: Switch to FDT parsing to get memory size 2025-02-26 17:11:09 +00:00
xilinx soc/xilinx/zynq7000: Initial Xilinx Zynq 7000 SoC bringup 2025-01-23 00:41:01 +00:00