coreboot/src
Luca Lai afbc9126f9 mb/trulo/var/pujjolo: Update GPIOs and probe SD card to fix S0ix suspend
Now we face the suspend could not enter s0ix issue.
So according to the schematics 627075_TWL PCH GPIO_Pujjolo_1th version
_20250527.xlsx to change gpio setting and hook up the SD card reader
via fwconfig to fix the issue.

Change :
1. gpio GPP_D8(SD_CLKREQ_ODL) to native function 1
2. add probe sd card.

BUG=b:422600523
BRANCH=none
TEST=Build and boot to OS. Verify powerd_dbus_suspend could enter S0ix

Change-Id: Iaa5a653608316ca8cb1e34429d30a2ebfdf7a1e9
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88050
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-06-16 15:18:40 +00:00
..
acpi Revert "acpi,Makefile: Add preload_acpi_dsdt" 2025-04-14 13:55:42 +00:00
arch arch/x86: Unify GDT entries 2025-05-08 12:29:24 +00:00
commonlib treewide: Work around GCC 15 Werror=unterminated-string-initialization 2025-06-09 07:19:09 +00:00
console console/i2c_smbus: Allow to send data w/o register offset 2024-07-11 00:06:22 +00:00
cpu cpu/intel/haswell: Export PCODE mailbox functions 2025-05-27 15:07:25 +00:00
device device/device_util.c: Complete function documentation 2025-06-15 12:55:59 +00:00
drivers drivers/efi/efivars: Change printk level from ERROR to DEBUG 2025-06-13 15:25:45 +00:00
ec ec/google: Add support for Realtek EC in ChromeOS EC 2025-06-07 15:03:35 +00:00
include soc/intel/pantherlake: Add support for the H204 SKU 2025-06-09 14:59:37 +00:00
lib treewide: Assume FMAP_SECTION_FLASH_START = 0 2025-04-18 14:57:05 +00:00
mainboard mb/trulo/var/pujjolo: Update GPIOs and probe SD card to fix S0ix suspend 2025-06-16 15:18:40 +00:00
northbridge Haswell NRI: Measure per-task execution time 2025-06-11 13:25:59 +00:00
sbom src, util: Clean up makefile.inc in text, help & comments 2024-01-26 20:15:18 +00:00
security security/vboot: Back up CMOS data later boot phase 2025-06-05 13:36:19 +00:00
soc soc/intel/cmd/blk/cnvi: Correct conditional logic for CNVI readiness 2025-06-16 10:37:53 +00:00
southbridge sb/intel/lynxpoint: Add CFR objects for existing options 2025-04-25 14:24:47 +00:00
superio src/superio/nuvoton: Add HWM initialization code 2025-06-11 13:31:25 +00:00
vendorcode vc/intel/fsp/ptl: Update PTL header files to FSP 3182_01 2025-06-13 01:47:44 +00:00
Kconfig security/vboot: Back up CMOS data later boot phase 2025-06-05 13:36:19 +00:00