Hung-Te Lin ae83564cdd tegra124: Revise Memory Controller registers structure definition. ... To implement memory initialization without BCT, we need more details of memory controller registers (mc). Note some register names have been changed, so Nyan mainboard VPR code is also modified. BUG=none TEST=emerge-nyan chromeos-coreboot-nyan # successfully. Change-Id: I179aa41c5a6419fc94cc3343ff23080d1db19ca2 Reviewed-on: https://chromium-review.googlesource.com/182992 Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org>		2014-01-22 04:52:12 +00:00
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arch	arm: Thumb ALL the things!	2014-01-14 03:29:48 +00:00
console	ARM: Generalize armv7 as arm.	2013-10-02 09:18:44 +00:00
cpu	cpu/intel: allow non-packaged scoped turbo setting	2014-01-15 04:52:13 +00:00
device	pnp: Allow setting of misc register 0xf4 in device tree	2013-12-20 00:37:38 +00:00
drivers	Haswell/falco/peppy/slippy: continue to clean up FUI.	2013-12-19 01:17:37 +00:00
ec	chromeec: add function to reboot on unexpected image	2014-01-10 00:11:54 +00:00
include	baytrail: snapshot power state in romstage	2014-01-09 20:15:55 +00:00
lib	baytrail: snapshot power state in romstage	2014-01-09 20:15:55 +00:00
mainboard	tegra124: Revise Memory Controller registers structure definition.	2014-01-22 04:52:12 +00:00
northbridge	peppy and falco: set panel power timings in northbridge, using devicetree, not mainboards	2013-12-23 08:55:32 +00:00
soc	tegra124: Revise Memory Controller registers structure definition.	2014-01-22 04:52:12 +00:00
southbridge	libpayload: find source of input characters	2014-01-19 04:15:03 +00:00
superio	pnp: Allow setting of misc register 0xf4 in device tree	2013-12-20 00:37:38 +00:00
vendorcode	chromeos: add VBOOT_REFCODE_INDEX option	2013-12-17 21:27:07 +00:00
Kconfig	armv8: add support for armv8 cpu	2014-01-07 02:48:47 +00:00