Not all ARM systems need "BL1", and the layout of BL* and bootblock may be
different (ex, Exynos 5250 may use a new BL1 with variable length checksum
header).
To support that better, define the real base address (and ROM offset) of boot
block, and then we can post-processing ROM image file by filling data / checksum
and any other information.
BUG=none
TEST=manual: emerge-daisy chromeos-coreboot-snow;
emerge-peach_pit chromeos-coreboot-peach_pit
BRANCH=none
Change-Id: I9b3ee083c2edac64a653d5d7dffc123d252878d7
Reviewed-on: https://gerrit.chromium.org/gerrit/58342
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
51 lines
1.3 KiB
Text
51 lines
1.3 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2006 Advanced Micro Devices, Inc.
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* Copyright (C) 2008-2010 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* We use ELF as output format. So that we can debug the code in some form. */
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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TARGET(binary)
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SECTIONS
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{
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ROMLOC = CONFIG_BOOTBLOCK_BASE;
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/* This section might be better named .setup */
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.rom ROMLOC : {
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_rom = .;
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*(.start);
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*(.id);
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*(.text);
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*(.text.*);
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*(.rom.text);
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*(.rom.data);
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*(.rom.data.*);
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*(.rodata.*);
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_erom = .;
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} = 0xff
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/DISCARD/ : {
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*(.comment)
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*(.note)
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*(.comment.*)
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*(.note.*)
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*(.ARM.*)
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}
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}
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