Patrick Rudolph 9e5c7eb3f8 soc/amd/glinda: Add XGBE devices ... Some specific Glinda SoCs support dual 10G PCI ethernet devices. Add defines and chipset entries for XGBE0 and XGBE1. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I7e3bb1819165a7c2f4284b76450f831bb99b1ad3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/90416 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2025-12-09 16:20:18 +00:00
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cezanne	soc/amd/*/memmap.c: Report FCH MMIO regions as reserved	2025-12-01 13:56:56 +00:00
common	soc/amd/common/fsp: Fill in DIMM voltages	2025-12-09 13:24:25 +00:00
genoa_poc	soc/amd: add ACPI code for I3C controller	2025-12-01 19:41:52 +00:00
glinda	soc/amd/glinda: Add XGBE devices	2025-12-09 16:20:18 +00:00
mendocino	soc/amd: add ACPI code for I3C controller	2025-12-01 19:41:52 +00:00
phoenix	soc/amd: add ACPI code for I3C controller	2025-12-01 19:41:52 +00:00
picasso	soc/amd/*/memmap.c: Report FCH MMIO regions as reserved	2025-12-01 13:56:56 +00:00
stoneyridge	soc/amd/stoneyridge: Generate SATA ACPI registers at runtime	2025-11-14 16:28:19 +00:00
turin_poc	soc/amd/turin_poc: Add Turin SoC structure as a copy of genoa_poc	2025-10-24 21:38:41 +00:00