This patch adds code to initialize the two DWC3 USB host controllers and their associated PHYs to the IPQ806x SoC (closely imitating the existing DWC3 implementation for Exynos5), and uses them to initialize USB on the Storm mainboard. BUG=chrome-os-partner:29375 TEST=Hack up netboot to get around missing SPI flash, load a file over TFTP. Hack a storage read into the storage attach function, dump the data and confirm that it looks right. Enable USB debugging and confirm 3.0 devices get enumerated at SuperSpeed (mostly). Change-Id: Iaf7b96bef994081ca222b7de9d8e8c49751d3f1d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/202157 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> |
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| .. | ||
| arch | ||
| console | ||
| cpu | ||
| device | ||
| drivers | ||
| ec | ||
| include | ||
| lib | ||
| mainboard | ||
| northbridge | ||
| soc | ||
| southbridge | ||
| superio | ||
| vendorcode | ||
| Kconfig | ||