coreboot/src/soc
Aaron Durbin 8d5795fbff tegra132: split memory range querying to above/below 4GiB
The address map code was originally assuming all carveouts would
be packed together in the upper end of the physical memory
address space. However, the trust zone carveout is always in the
32-bit address space. Therefore, one needs to query memory ranges
by above and below 4GiB with the assumption of carveouts being
packed at the top of *each* resulting range.

BUG=chrome-os-partner:30572
BRANCH=None
TEST=Built and ran through coreboot on rush.

Change-Id: Iab134a049f3726f1ec41fc6626b1a6683d9f5362
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/208101
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
2014-07-16 19:21:47 +00:00
..
intel broadwell: Move platform report output after power state is read 2014-07-16 07:12:21 +00:00
nvidia tegra132: split memory range querying to above/below 4GiB 2014-07-16 19:21:47 +00:00
qualcomm storm: allow to override CBFS_SIZE configuration setting 2014-07-16 07:13:44 +00:00
samsung i2c: Add software_i2c driver for I2C debugging and emulation 2014-05-19 20:34:31 +00:00
Kconfig coreboot: Move ARCH_* from board/Kconfig to cpu or soc Kconfig. 2014-05-08 22:36:06 +00:00
Makefile.inc ipq806x: Add generic support skeleton for ipq806x 2014-03-25 00:32:03 +00:00