coreboot/src/southbridge
Angel Pons 67e3579d61 sb/intel/lynxpoint: Enable PCIe Relaxed Order
Follow Lynx Point PCH reference code version 1.9.1 to enable PCIe
Relaxed Order.

Change-Id: If7ba4e826adfc8c220ecc68c4a456fbe3cb99667
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57504
Reviewed-by: Lean Sheng Tan <tanleansheng@outlook.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2025-09-25 16:06:18 +00:00
..
amd treewide: Assume FMAP_SECTION_FLASH_START = 0 2025-04-18 14:57:05 +00:00
intel sb/intel/lynxpoint: Enable PCIe Relaxed Order 2025-09-25 16:06:18 +00:00
ricoh/rl5c476 tree: Remove blank lines before '}' and after '{' 2024-04-11 19:19:08 +00:00
ti tree: Remove blank lines before '}' and after '{' 2024-04-11 19:19:08 +00:00