Vadim Bendebury 75decceccd ipq8064: Make clock code build in coreboot ... Include clock.c in the appropriate coreboot stages, modify the code to build cleanly. Use proper pointer cast in .h files. BUG=chrome-os-partner:27784 TEST='emerge-storm coreboot' still succeeds Change-Id: I227c871b17e571f6a1db3ada3821dbb1ee884e59 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196407		2014-04-23 22:59:54 +00:00
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arch	BACKPORT: x86 I/O APIC: Make functions io_apic_{read,write}() public	2014-04-23 02:44:28 +00:00
console	ipq8064: prepare UART driver for use in coreboot	2014-04-23 20:50:26 +00:00
cpu	x86: Set BOOT_MEDIA_SPI_BUS	2014-04-15 05:41:46 +00:00
device	Remove stale char[] initialization causing unaligned memory access	2014-03-14 03:44:47 +00:00
drivers	BACKPORT: x86 I/O APIC: Make functions io_apic_{read,write}() public	2014-04-23 02:44:28 +00:00
ec	i2c: Replace the i2c API.	2014-04-10 06:05:01 +00:00
include	reg_script: Fix bug in IO macros	2014-04-23 02:50:42 +00:00
lib	ipq8064: prepare UART driver for use in coreboot	2014-04-23 20:50:26 +00:00
mainboard	nyan: Add jtag config file	2014-04-23 02:53:21 +00:00
northbridge	spi: Remove unused parameters from spi_flash_probe and setup_spi_slave.	2014-04-01 23:21:22 +00:00
soc	ipq8064: Make clock code build in coreboot	2014-04-23 22:59:54 +00:00
southbridge	x86: Initialize SPI controller explicitly during PCH init	2014-04-17 16:42:37 +00:00
superio
vendorcode	chromeos: Add empty functions when CONFIG_CHROMEOS is disabled	2014-04-23 02:47:40 +00:00
Kconfig