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coreboot/src/northbridge/amd
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WANG Siyuan 6762a8b85e AMD PI agesawrapper: add PSPP (PCIe Speed Power Policy) interface 
PSPP policy is defined in 3rdparty/blobs/pi/amd/*/AGESA.h
/// PCIe PSPP Power policy
typedef enum  {
  PsppDisabled,                                           ///< PSPP disabled
  PsppPerformance = 1,                                    ///< Performance
  PsppBalanceHigh,                                        ///< Balance-High
  PsppBalanceLow,                                         ///< Balance-Low
  PsppPowerSaving,                                        ///< Power Saving
  MaxPspp                                                 ///< Max Pspp for boundary check
} PCIE_PSPP_POLICY;

Change-Id: I7fe735cddea94a83e38d856a3de1f27735467a28
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10461
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-06-23 01:10:52 +02:00
..
agesa AMD OemS3Save: refactor for Merlin Falcon 2015-06-22 22:27:14 +02:00
amdfam10 Move remap_bsp_lapic to AMD specific code 2015-06-13 21:06:52 +02:00
amdht Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
amdk8 Move remap_bsp_lapic to AMD specific code 2015-06-13 21:06:52 +02:00
amdmct northbridge/amd/amdmct: Honor MMCONF_BASE_ADDRESS 2015-06-10 05:33:53 +02:00
cimx Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
gx2 Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
lx Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
pi AMD PI agesawrapper: add PSPP (PCIe Speed Power Policy) interface 2015-06-23 01:10:52 +02:00