coreboot/src
Jonathan A. Kollasch 619781493a mainboard/msi/ms7135: DSDT: fix PCI and AGR interrupts
Tested with interrupting AGP card in AGR slot.
PCI slots tested with 3-function OHCI/EHCI USB 2.0 card,
covering the INTA-INTC lines in each.

Change-Id: I0f8aeba90890a76a7cf9cbee9be7bcf919d1e39a
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10644
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-29 18:28:59 +02:00
..
acpi acpi/sata: add generic sata ssdt port generator 2015-06-07 01:24:47 +02:00
arch x86: Move architecture selection from linker script to Makefile.inc 2015-06-26 22:44:10 +02:00
console consoles: remove unused infrastructure 2015-05-26 19:02:54 +02:00
cpu cpu: x86 port to 64bit 2015-06-20 18:16:54 +02:00
device ddr3: add missing newline 2015-06-23 01:50:33 +02:00
drivers Kconfig: Remove unnecessary and incorrect MRC_CACHE symbols 2015-06-27 02:47:39 +02:00
ec lenovo: Move pc_keyboard_init to h8 init. 2015-05-29 07:45:55 +02:00
include cpu/x86: Add more MTRR symbols 2015-06-24 17:03:29 +02:00
lib prog_loader: Play nice with gc-sections 2015-06-26 22:43:46 +02:00
mainboard mainboard/msi/ms7135: DSDT: fix PCI and AGR interrupts 2015-06-29 18:28:59 +02:00
northbridge intel raminit: check correct registers in channel_test 2015-06-28 22:42:11 +02:00
soc rockchip/rk3288: complete vboot configuration and move to SoC 2015-06-26 23:30:39 +02:00
southbridge amd/pi/hudson: Fill ROMSIG with 0xFF instead of 0 2015-06-25 04:06:59 +02:00
superio superio: use common x86 code on x86-64 2015-06-22 07:36:09 +02:00
vendorcode google/chromeos: always enable VBOOT_VERIFY_FIRMWARE with CHROMEOS 2015-06-26 23:30:13 +02:00
Kconfig southbridge/intel: Create common IFD Kconfig and Makefile 2015-06-23 22:48:45 +02:00