coreboot/src/soc/mediatek
Jarried Lin 5411e1a6cf soc/mediatek/mt8196: Add pi_img loader in ramstage
This patch includes loading pi_img through CBFS and passing parameters
of pi_img to mtk_fsp for parsing.

BUG=b:373797027
TEST=Build pass. boot ok.
Locd pi_img with following logs:
CBFS: Found 'pi_img.img' @0xb2340 size 0x9620 in mcache @0xfffdd440
read SPI 0x4b43a0 0x9620: 2946 us, 13045 KB/s, 104.360 Mbps
VB2:vb2_digest_init() 38432 bytes, hash algo 2, HW acceleration enabled
mtk_init_mcu: Loaded (and reset) pi_img.img in 3 msecs (180421 bytes)

Change-Id: I571243c3115f5cd005fac88eb740c643e936fca9
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86161
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2025-01-27 23:58:02 +00:00
..
common soc/mediatek/mt8196: Add pi_img loader in ramstage 2025-01-27 23:58:02 +00:00
mt8173 soc/mediatek/common: Rename GPT_MHZ to TIMER_MHZ for readability 2024-12-21 16:09:23 +00:00
mt8183 tree: Remove unused <assert.h> 2024-11-19 00:40:04 +00:00
mt8186 soc/mediatek: Allow specifying multiple EINT base registers 2025-01-18 13:09:40 +00:00
mt8188 soc/mediatek: Allow specifying multiple EINT base registers 2025-01-18 13:09:40 +00:00
mt8189 soc/mediatek/mt8189: Enable timer compensation v2.5 2024-12-24 11:22:38 +00:00
mt8192 soc/mediatek: Allow specifying multiple EINT base registers 2025-01-18 13:09:40 +00:00
mt8195 soc/mediatek: Allow specifying multiple EINT base registers 2025-01-18 13:09:40 +00:00
mt8196 soc/mediatek/mt8196: Add pi_img loader in ramstage 2025-01-27 23:58:02 +00:00