Julius Werner 8f34fdfab3 Remove <swab.h> and swabXX() functions ... GCC generates correct code for __builtin_bswapXX() on all architectures, including ArmV4. It seems that whatever bug caused this to not work back in commit 879ea7fce8 ("endian: Replace explicit byte swapping with compiler builtin") has been fixed now. We can eliminate the swabXX() functions and simplify the code. All instances that had been calling these functions directly should have been using real endianness conversions anyway. Change-Id: I19713fd009aa5c0e01c4a42e0cf012364d6bed60 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90438 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>		2025-12-12 07:09:45 +00:00
..
cezanne	soc/amd/*/memmap.c: Report FCH MMIO regions as reserved	2025-12-01 13:56:56 +00:00
common	Remove <swab.h> and swabXX() functions	2025-12-12 07:09:45 +00:00
genoa_poc	soc/amd: add ACPI code for I3C controller	2025-12-01 19:41:52 +00:00
glinda	soc/amd/glinda: Set FSP UPDs from devicetree for USB4	2025-12-09 16:26:13 +00:00
mendocino	soc/amd: add ACPI code for I3C controller	2025-12-01 19:41:52 +00:00
phoenix	soc/amd: add ACPI code for I3C controller	2025-12-01 19:41:52 +00:00
picasso	soc/amd/*/memmap.c: Report FCH MMIO regions as reserved	2025-12-01 13:56:56 +00:00
stoneyridge	soc/amd/stoneyridge: Generate SATA ACPI registers at runtime	2025-11-14 16:28:19 +00:00
turin_poc	soc/amd/turin_poc: Add Turin SoC structure as a copy of genoa_poc	2025-10-24 21:38:41 +00:00