coreboot/src/soc
Werner Zeh 7729da04f8 UPSTREAM: fsp_broadwell_de: Correct access to SIRQ_CNTL register
The serial IRQ configuration register is only 8 bit wide so switch the
PCI access from 16 bits to 8 bits.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16534
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Ia9fbc02251e00b31440bf103e2afc2ff285b7f2e
Reviewed-on: https://chromium-review.googlesource.com/384961
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-13 22:19:51 -07:00
..
broadcom/cygnus UPSTREAM: soc/broadcom/cygnus/ddr_init.c: Correct typo in POWER ON and POWER OK. 2016-09-04 23:28:27 -07:00
dmp/vortex86ex UPSTREAM: src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-08-04 23:37:59 -07:00
imgtec/pistachio drivers/uart: Use uart_platform_refclk for all UART models 2016-05-09 18:45:44 +02:00
intel UPSTREAM: fsp_broadwell_de: Correct access to SIRQ_CNTL register 2016-09-13 22:19:51 -07:00
marvell UPSTREAM: src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-08-04 23:37:59 -07:00
mediatek/mt8173 UPSTREAM: src/soc: Add required space before opening parenthesis '(' 2016-09-04 19:36:49 -07:00
nvidia UPSTREAM: commonlib: move DIV_ROUND macros from nvidia/tegra 2016-09-08 17:57:23 -07:00
qualcomm UPSTREAM: src/soc: Add required space before opening parenthesis '(' 2016-09-04 19:36:49 -07:00
rdc/r8610 rdc/r8610: Move to src/soc 2016-05-05 20:08:58 +02:00
rockchip rockchip: spi: Add support for 16-bit APB reads 2016-09-09 02:58:48 -07:00
samsung UPSTREAM: src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-08-04 23:37:59 -07:00
ucb/riscv UPSTREAM: soc/ucb/riscv: select BOOTBLOCK_CONSOLE 2016-08-15 18:36:13 -07:00