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UPSTREAM: fsp_broadwell_de: Correct access to SIRQ_CNTL register

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The serial IRQ configuration register is only 8 bit wide so switch the
PCI access from 16 bits to 8 bits.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16534
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Ia9fbc02251e00b31440bf103e2afc2ff285b7f2e
Reviewed-on: https://chromium-review.googlesource.com/384961
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Werner Zeh 2016-09-08 07:27:29 +02:00 • committed by chrome-bot
commit 7729da04f8
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/fsp_broadwell_de/southcluster.c
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@ -215,7 +215,7 @@ static void sc_init(struct device *dev)
PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
/* Program Serial IRQ register. */
pci_write_config16(dev, 0x64, 0xd0);
pci_write_config8(dev, 0x64, 0xd0);
sc_pirq_init(dev);
write_pci_config_irqs();