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UPSTREAM: soc/ucb/riscv: select BOOTBLOCK_CONSOLE

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BUG=None
BRANCH=None
TEST=None

Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16158
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Change-Id: I847d7686dec04e9fae7db13d53adc8ca32c56f3a
Reviewed-on: https://chromium-review.googlesource.com/370705
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Jonathan Neuschäfer 2016-08-11 22:49:14 +02:00 • committed by chrome-bot
commit 195924d6ac
1 changed files with 1 additions and 0 deletions
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src/soc/ucb/riscv/Kconfig
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@ -4,6 +4,7 @@ config SOC_UCB_RISCV
select ARCH_VERSTAGE_RISCV
select ARCH_ROMSTAGE_RISCV
select ARCH_RAMSTAGE_RISCV
select BOOTBLOCK_CONSOLE
bool
default n