coreboot/src/northbridge/intel
Angel Pons 4a4ad2b1e6 haswell NRI: Initialise MPLL
Add code to initialise the MPLL (Memory PLL). The procedure is similar
to the one for Sandy/Ivy Bridge, but it is not worth factoring out.

Change-Id: I978c352de68f6d8cecc76f4ae3c12daaf4be9ed6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64184
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-12-10 09:37:51 +00:00
..
common
e7505 cpu/x86: Make 1GB paging the default 2024-06-05 20:31:03 +00:00
gm45 nb/intel/gm45/northbridge.c: Use config_of_soc() 2024-10-07 20:37:35 +00:00
haswell haswell NRI: Initialise MPLL 2024-12-10 09:37:51 +00:00
i440bx cbmem_top: Change the return value to uintptr_t 2024-07-10 12:55:46 +00:00
i945 i945: Use nullptr instead of NULL 2024-10-14 15:31:08 +00:00
ironlake nb/intel/*: Match ACPI with resource allocation 2024-08-05 08:28:44 +00:00
pineview nb/intel/*: Match ACPI with resource allocation 2024-08-05 08:28:44 +00:00
sandybridge nb/intel/*: Explicitly include static.h for config_of_soc 2024-10-07 20:32:33 +00:00
x4x nb/intel/*: Match ACPI with resource allocation 2024-08-05 08:28:44 +00:00