coreboot/src
Duncan Laurie 2446b35578 broadwell: Update ACPI devices
Broadwell devices have new _HID values, although the kernel
drivers do not seem to treat them differently right now.
ADSP was using an incorrect _HID for lynxpoint devices which
conflicted with the I2C controller.

The SerialIO ACPI devices need custom methods to put the
controller in D0 or D3 state.  These need to use the PCIe
config space that is mirrored in BAR1.

Additionally the device should not be put into D3hot state
until after setup is complete, which also means that it needs
to use the BAR instead of PCIe config cycles.

BUG=chrome-os-partner:28234
TEST=boot with devices in ACPI mode and ensure the kernel
I2C driver can bring them out of D3 and initialize them properly.
Also ensure that the driver puts the controller in D3 state
when there is no activity on the bus.

Change-Id: I82a860fceb2a32d9975f93dedcaaf2a48e354d1c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/201080
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2014-05-24 00:38:51 +00:00
..
arch coreboot arm64: Add support for arm64 into coreboot framework 2014-05-15 23:52:58 +00:00
console Add stage information to coreboot banner 2014-05-14 20:49:21 +00:00
cpu coreboot: Introduce stage-specific architecture for coreboot 2014-05-09 04:41:47 +00:00
device i2c: Add software_i2c driver for I2C debugging and emulation 2014-05-19 20:34:31 +00:00
drivers SPI: Add Eon EN25S64 support. 2014-05-09 22:00:56 +00:00
ec chromeos: Unconditionally clear the EC recovery request 2014-05-07 03:33:49 +00:00
include i2c: Add software_i2c driver for I2C debugging and emulation 2014-05-19 20:34:31 +00:00
lib cbmem: use a single id to name mapping table 2014-05-14 22:53:16 +00:00
mainboard bayleybay: modify board related settings for baytrail CRB 2014-05-23 05:01:40 +00:00
northbridge coreboot: Rename coreboot_ram stage to ramstage 2014-05-07 23:30:23 +00:00
soc broadwell: Update ACPI devices 2014-05-24 00:38:51 +00:00
southbridge coreboot: Rename coreboot_ram stage to ramstage 2014-05-07 23:30:23 +00:00
superio pnp: Allow setting of misc register 0xf4 in device tree 2013-12-20 00:37:38 +00:00
vendorcode elog: Add function to log boot reason in ChromeOS case 2014-05-15 05:26:46 +00:00
Kconfig coreboot arm64: Add support for arm64 into coreboot framework 2014-05-15 23:52:58 +00:00