Jimmy Zhang 3fcb3e8299 ryu: Update BCT to Max Frequency 924MHz ... Replace previous 528MHz BCT. This BCT contains four entries as below: 0: Samsung 1: Hynix 2: Micron 3: (spare) 528MHz Micron BUG=none BRANCH=none TEST=Built and tested on Micron LPDDR. Change-Id: I49e18ca8dc69f2ce9ded71f4f55c02a8b91f92b2 Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-on: https://chromium-review.googlesource.com/211479 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Tom Warren <twarren@nvidia.com>		2014-08-09 00:20:18 +00:00
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arch	arm: add _end symbol to bootblock.ld	2014-08-04 16:34:12 +00:00
console	vboot2: implement select_firmware for pre-romstage verification	2014-06-30 18:45:09 +00:00
cpu	haswell: Update microcode revision	2014-07-29 04:37:18 +00:00
device	i2c: Add software_i2c driver for I2C debugging and emulation	2014-05-19 20:34:31 +00:00
drivers	spi: Support Macronix MX25U6435F SPI ROM.	2014-08-07 22:45:49 +00:00
ec	chromeec: provide proto v3 over i2c support	2014-08-07 22:38:07 +00:00
include	Restore name of the function reading tertiary GPIO states	2014-08-08 03:11:27 +00:00
lib	Restore name of the function reading tertiary GPIO states	2014-08-08 03:11:27 +00:00
mainboard	ryu: Update BCT to Max Frequency 924MHz	2014-08-09 00:20:18 +00:00
northbridge	coreboot: Rename coreboot_ram stage to ramstage	2014-05-07 23:30:23 +00:00
soc	tegra132: never recover cbmem from romstage	2014-08-08 22:03:33 +00:00
southbridge	coreboot: Rename coreboot_ram stage to ramstage	2014-05-07 23:30:23 +00:00
superio	pnp: Allow setting of misc register 0xf4 in device tree	2013-12-20 00:37:38 +00:00
vendorcode	vboot: fix vboot_load_ramstage()	2014-08-05 02:39:09 +00:00
Kconfig	Enable publishing of board ID where supported	2014-07-30 23:41:23 +00:00